Sampa

DAQ running instructions can be found here:

CLON Standard Procedures

Documentation:

SAMPA V3 full manual

SAMPA V5 Data Sheet

sampa/felix register access instructions from Takao Sakaguchi (Mar 11, 2022)

From Irakli (March 17, 2021):

  The main shortcoming in the Sampa V5 is its relatively low dynamic range.
You can have linearity range up to 66 fC (30 mV/Fc gain) or up to 100 fC (20 mV/fC gain).
Unfortunately the 4 mV/fC gain (500 fC range) has been removed from the Sampa V5.
(It was in Sampa V4 but characterized for positive signals).
  The working point of our current Dream electronics is 200 fC dynamic range.
And if needed we can switch to  600 fC or 100 fC.
  This means that with Sampa V5 you can get quite often in a non-linear range with saturating ADC counts.
It does not mean that the very frontend stage of Sampa will not be able to work at high hit rate.
It is very robust and can sustain high currents.
It is just that you will not be able to recover timing from the pulse maximum.
The rising edge should be OK though, if sampling rate is fast enough to have 3 samples per front.
  The sampling rate of Sampa is 10 or 20 MHz.
Current Dream electronics operate at 25 MHz.
  Concerning the peaking time we are almost there.
Sampa can work with 160 ns peaking time and we are using 180 ns peaking time.
But Dream has mush more peaking time choice - can be handy in certain cases to get better S/N.
  Concerning the input capacitance.
Normally Sampa V5 is designed for input capacitance ranges of several tens of pF.
The MVT strip capacitances vary from  80 to 120 pF.
If you will conserve the cables you will need to add 70 to 100pF.
Sampa will see 150 pF to 200 pF capacitance.
Measurements show (ati Jlab by the way) that Sampa looks stable for this capacitences.
But what I expect that for theses capacitances the 20 mV/fC transfer function will be lowered by about 20% and 25% respectively.
With increase of the noise level, the S/N ration will suffer, for sure, but may still remain fine, because on can increase detector gain.
(Attention though, high detector gain means high probability of ADC saturation).

LV control (PL506 WIENER supply in EEL/125, 'mmtblv', 129.57.86.105)

caput B_HW_MMTBLV_Sl0_Ch3:switch 0
caput B_HW_MMTBLV_Sl0_Ch3:v_set 4.0
caput B_HW_MMTBLV_Sl0_Ch3:i_set 1.5
caput B_HW_MMTBLV_Sl0_Ch3:switch 1

caput B_HW_MMTBLV_Sl0_Ch4:switch 0
caput B_HW_MMTBLV_Sl0_Ch4:v_set 2.0
caput B_HW_MMTBLV_Sl0_Ch4:i_set 5.5
caput B_HW_MMTBLV_Sl0_Ch4:switch 1

caget B_HW_MMTBLV_Sl0_Ch3:i_set:fbk
                          v_set:fbk
                          i_rd
                          v_term
                          v_sens
caget B_HW_MMTBLV_Sl0_Ch4:i_set:fbk
                          v_set:fbk
                          i_rd
                          v_term
                          v_sens

SNMP for PL506 described here: PL506 manual with SNMP description

Felix modile load

As root in the folder:
/usr/clas12/release/1.4.0/coda/src/tpc-devel_ben/dam_pcie/src
run:
insmod dam_pcie.ko

HV control (channel 00 must be 500V, channel 06 - 600V): run clascss as clasrun@clonsl1, menu screenshot: MM HV Control PMT HV Control