VHDL programming

Basic rules for V1495-based CLAS triggers

In general VHDL files contains following sections:

1. Includes, for example:

library ieee;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
use IEEE.Std_Logic_unsigned.all;

2. Entity declaration, includes name and IO signals description

entity HallBTrigger is
        port(
               A        : IN     std_logic_vector (31 DOWNTO 0);  -- In A (32 x LVDS/ECL)
               -- describe all IO signals here
       );
end HallBTrigger;

3. Actual body beginning:

architecture Synthesis of HallBTrigger is

4. Description of another entity (just describes, actual include will be done below)

       component SectorPeripheral is
               generic(
			BASE_ADDR	: std_logic_vector(15 downto 8)
		);
		port(
			RESET			: in std_logic;
                       -- describe all IO signals here
		);
	end component;

5. Internal signals description (internal for this entity):

	signal PLLCLK			: std_logic;
	signal HEART_BEAT_CNT	: std_logic_vector(25 downto 0) := "00000000000000000000000000";
	signal USER_DIN			: std_logic_vector(31 downto 0);

6.