JLAB Discriminators

Manual for 16-Channel Discriminator/Scaler VME Module (by J.Proffit), 20-Nov-2002, in (pdf)

Manual for New 16-Channel Discriminator/Scaler VME Module (draft by Ben Raydo), 6-Mar-2009, in (pdf)

Manual for New 16-Channel Discriminator/Scaler VME Module (rev.B by Ben Raydo), 28-May-2010, in (pdf)

Manual for New 16-Channel Discriminator/Scaler VME Module (rev.C by Ben Raydo), 11-Feb-2011, in (pdf)

Firmware update

dscInit(0xd10000,0x10000,2) - initialize 2 boards
dscUpdateFirmwareAll("/usr/clas/devel/coda/src/rol/code.s/vmeDSC_firmware_v1_8.bin")

Current firmware: vmeDSC_firmware_v1_8.bin

Development history

First version was developed by James Proffitt and is used in tagger system. It was tested by Sergey Pozdnyakov. Results of tests are presented on the next few slides:

• Width distribution ( eps pdf)

• Threshold distribution ( eps pdf)

• Resolution of Leading Edge for JLab Discr. ( pdf eps)

• Resolution of Leading Edge for LeCroy 2313 Discr. (for compare) ( pdf eps)

• Resolution of Trailing Edge for JLab Discr. ( pdf eps)

Following changes were recommended to make that board suitable for CLAS12:

• remove preamplifiers (at least reduce gain): can be done by not-installing some components; different amplifiers can be installed

• mask outputs

• add test input: directly to digital side

• individual channel thresholds, min 10 mV - real

• add second output connector (or high dense connector ?): yes

• different thresholds for output 1 and output 2 (optional; maybe sacrofise individual threshold, maybe groups of 4 etc)

• individual programmable width step: 8ns -> 4ns, the less the better; max=100ns; non-updating mode

• channel-based output delays for trigger output connector - optional, 500ns max

• 32-channel: will try (backplane board ?)

• fast enough: min 150MHz

• internal delay (20 ns is Ok)

• thermodrift - to be studied

• remove monitor

• not-stop scaler readout - optional

• keep gate/veto (2 inputs)

• OR for trigger output (NIM)

• VME readout: write/read all registers, A32/D64 with DMA

As on October 11, 2007 the possibility of board redesign was discussed with Volker, Chris and Stan Majewski, and we are waiting for Stan's final word.

Nov 16, 2007 James responded, asking for details. Sergey responded to Volker and James.

Apr 16, 2008: waiting for management to find money to pay James to do a job.

June 4, 2008: meeting with James and two Sergey's, first discussion on new design and work schedule.

January 28, 2009: CLON meeting with Chris, decided to refresh the project

June 3, 2009: Ben presented first results with 2-channel populated prototype (pdf). Next step will be to give prototype to Sergey P. for testing, sometime in the end of June.

Sep 30, 2009: Sergey Pozdnyakov completed first tests, pictures: TDC output resolution ch0-7, TDC output resolution ch8-15, TRG output resolution ch0-7, TRG output resolution ch8-15.