JLAB FADC250

Preliminary documentation:

Sep 1, 2011 registers description in V2 Programming (pdf)

Some documentation received on Sep 12, 2011 from Bryan Moffit:

V2 FPGA (pdf)

Signal Control Module (pdf)

Some documentation for V1 FADC:

V1 data format (pdf)

V1 Programming ((pdf)

Test results - pulser with realistic shape

• FADC250 Signal: one channel - 100 events; width because of trigger jitter ?

fadc250.SB.doublepeak.pdf ( pdf)

• FADC250 Signal: one channel - one event

fadc250.SB.onepeak.pdf ( pdf)

• FADC250 Signals, offset=3300 for all channels: 16 channels - one event. Note: channel 6 - dead, channel 15 - overflow due to high offset

fadc250.SB.16ch.pdf ( pdf)

• FADC250 Signals, offset=3200 for all channels: 16 channels - one event. Note: channel 6 - dead

fadc250_16ch.10452.pdf ( pdf)

• FADC250 Baseline (Pedestal) measurements: presentation in time-line and distribution, based on about 60 hours running with 1 Hz event rate

fadc250_16ch_bl_ped.10452.pdf ( pdf)

• FADC250 Offset Calibration

fadc250_16ch_bl_slope.10453.pdf ( pdf)