Scratch
mgetty
Sergey --- does this help you ? Today marked the 3rd week since this case was opened....
Paul
Original Message --------
Subject: CASE 66172087 Date: Wed, 28 Jan 2009 12:39:51 -0500 From: Roland 'butch' Morrissette - Sun Microsystems <Roland.Morrissette@sun.com> To: letta@jlab.org
Paul
Received this from engineering. Hopefully this is of some helpfull.
xdm is creating $HOME/.Xauthority file, xauth only reads it. In $HOME/.Xdefaults file try adding the following entry as an alternate location to see if it works.
DisplayManager.DISPLAY.userAuthDir
- /DISPLAY should be the actual display, like
/DisplayManager.host1:0.0.userAuthDir: /path/to/alternate/file
- (If this does not work and still $HOME/.Xauthority file gets written
try changing the permissions on $HOME/.Xauthority file to readonly)
Regards,
--
Roland 'Butch' Morrissette Sun Service OS Support Sun Microsystems, Inc.
phone: (781) 442-7112 email: roland.morrissette@sun.com (800)USA-4SUN (Reference your Case Id #)
My Working Hours : 8am-4pm ET, Monday thru Friday My Manager's Email: dawn.ball@sun.com
5126 303-6644
CLAS12 DC (Mac 14-nov-2007): 2 stereo, +-6 degrees, good resolution (1% dp/p, 1 mrad angle), six 6-layer superlayers, 112 wires per layer; reconstruction improvements: use double hits, use segment angle in road dictionary, early l-r ambig. resolution (now it resolved locally and then corrected after track reconstructed ?), find tracks with no TOF hit and cut off accidental tracks (using residials ?), derive off-diagonal terms in error matrix
SVT readout:
SVX4 - old chip 132ns clock, 40pipeline cells ->5.2us trigger latency; can select readout window like pipeline TDCs (position defined +-132us, window size 132ns fixed) initial part stored upto 4 events, they are rotating internally 32 bits per hit, 128 channels per chip, ... -> 3.2us per chip to get data from the chip to the buffer of 512 full events L2 pipeline 16us L1 latency from Amrit is 3us, Amrit will try to make it 4us Use the same clock as entire CLAS12 trigger system (256MHz)
FSSR 125ns instead of 132ns (built for BTev, never used) self-triggering, do not need L1ACCEPT, L2 pipe 16us can be implemented
SVX4 goes to review !!!
Generic DAQ drawing will be sent to Amrit in April