October 20, 2010 online meeting minutes: Difference between revisions
Jump to navigation
Jump to search
No edit summary |
No edit summary |
||
| Line 1: | Line 1: | ||
present: Sergey, Sergey, Eugene, Pawel, Nerses | present: Sergey Boyarinov, Sergey Pozdnyakov, Eugene Pasyuk, Pawel, Nerses | ||
1.PRIMEX2 | 1.PRIMEX2 status | ||
* Live time scalers: need 2 caen560 scalers, gated one must be gated by TS busy signal; addresses will be send to Sergey B. | * Live time scalers: need 2 caen560 scalers, gated one must be gated by TS busy signal; addresses will be send to Sergey B. | ||
Revision as of 10:10, 20 October 2010
present: Sergey Boyarinov, Sergey Pozdnyakov, Eugene Pasyuk, Pawel, Nerses
1.PRIMEX2 status
- Live time scalers: need 2 caen560 scalers, gated one must be gated by TS busy signal; addresses will be send to Sergey B.
- Amhendra Nahayan from Hall C took AC cable from croctest2, will return it in few weeks, phone 757-952-6126, nahayan@jlab.org (in Compton, Hall C)
- tage replacement:: have crte, have tdcs 1190, neew TI, need 34pin cable adapters, need one level translator, need back transition piece for co-processor, will put it on external cart temporary and eventualy remove FASTBUS TAGE crate; Sergey B. will try to get 34pin male connectors asap
- livetime from TS2 sometimes higher then 100%, need to understand and fix; correction function was taken out, seems no difference ?
- trigger bit 2 (OR from hycal) is jumping factor 3, every about 5 minutes, need to investigate, maybe analog sum from hycal or discriminator, will bring analog scheme output upstears and watch it (or use scope downstears); analog sums are UVA 120 boards