JLAB Discriminators: Difference between revisions

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* add test input: directly to digital side
* add test input: directly to digital side


* individual channel thresholds
* individual channel thresholds, min 10 mV - real


* add second output connector (or high dense connector ?): yes
* add second output connector (or high dense connector ?): yes


* individual programmable width step: 8ns -> 4ns, the less the better
* different thresholds for output 1 and output 2 (optional; maybe sacrofise individual threshold, maybe groups of 4 etc)


* delay ???
* individual programmable width step: 8ns -> 4ns, the less the better; max=100ns; non-updating mode


* 32-channel: will try
* channel-based output delays for trigger output connector - optional, 500ns max


* fast enough ???
* 32-channel: will try (backplane board ?)


* internal delay ??? (10-20 ns is Ok)
* fast enough: min 150MHz


* thermodrift ???
* internal delay (20 ns is Ok)
 
* thermodrift - to be studied


* remove monitor
* remove monitor


* not-stop scaler readout possible problem ???
* not-stop scaler readout - optional
 
* keep gate/veto (2 inputs)


* OR output (NIM, dECL ?)
* OR for trigger output (NIM)


* VME readout ???
* VME readout: write/read all registers, A32/D64 with DMA


As on October 11, 2007 the possibility of board redesign was discussed with Volker, Chris and Stan Majewski, and we are waiting for Stan's final word.
As on October 11, 2007 the possibility of board redesign was discussed with Volker, Chris and Stan Majewski, and we are waiting for Stan's final word.

Revision as of 10:36, 28 January 2009

First version was developed by James Proffitt and is used in tagger system. It was tested by Sergey Pozdnyakov. Results of tests are presented on the next few slides:

  • Threshold distribution ( eps pdf)
  • Resolution of Leading Edge for JLab Discr. ( pdf eps)
  • Resolution of Leading Edge for LeCroy 2313 Discr. (for compare) ( pdf eps)
  • Resolution of Trailing Edge for JLab Discr. ( pdf eps)

Manual: pdf.

Following changes were recommended to make that board suitable for CLAS12:

  • remove preamplifiers (at least reduce gain): can be done by not-installing some components; different amplifiers can be installed
  • mask outputs
  • add test input: directly to digital side
  • individual channel thresholds, min 10 mV - real
  • add second output connector (or high dense connector ?): yes
  • different thresholds for output 1 and output 2 (optional; maybe sacrofise individual threshold, maybe groups of 4 etc)
  • individual programmable width step: 8ns -> 4ns, the less the better; max=100ns; non-updating mode
  • channel-based output delays for trigger output connector - optional, 500ns max
  • 32-channel: will try (backplane board ?)
  • fast enough: min 150MHz
  • internal delay (20 ns is Ok)
  • thermodrift - to be studied
  • remove monitor
  • not-stop scaler readout - optional
  • keep gate/veto (2 inputs)
  • OR for trigger output (NIM)
  • VME readout: write/read all registers, A32/D64 with DMA

As on October 11, 2007 the possibility of board redesign was discussed with Volker, Chris and Stan Majewski, and we are waiting for Stan's final word.

Nov 16, 2007 James responded, asking for details. Sergey responded to Volker and James.

Apr 16, 2008: waiting for management to find money to pay James to do a job.

June 4, 2008: meeting with James and two Sergey's, first discussion on new design and work schedule.