October 15, 2008 online meeting minutes: Difference between revisions
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EPICS readout for scalers in both CLASTRIG2 and DVCSTRIG is working, scaler histograms and corresponding MEDM GUIs to be checked; normally all scalers will be reported in Hz; all quadrons counts equally | EPICS readout for scalers in both CLASTRIG2 and DVCSTRIG is working, scaler histograms and corresponding MEDM GUIs to be checked; normally all scalers will be reported in Hz; all quadrons counts equally | ||
Ben developed pattern test for the CLASTRIG2, extra v1495 board was installed in clastrig2 and connected to the main v1495, test was started from Windows GUI and passed successfully; DVCSTRIG test to be conducted - VERY IMPORTANT ! | Ben developed pattern test for the CLASTRIG2, extra v1495 board was installed in clastrig2 and connected to the main v1495, test was started from Windows GUI and passed successfully; DVCSTRIG test to be conducted - VERY IMPORTANT ! also wiil look at polarity of the optput cables | ||
trigger downloading scripts were adjusted, downloading/uploading works fine, uploading LUT still not implemented | trigger downloading scripts were adjusted, downloading/uploading works fine, uploading LUT still not implemented | ||
L2 to be tested | L2 to be tested | ||
Revision as of 09:03, 15 October 2008
present: Sergey Boyarinov, Valeri, Ben, Chris Cuevas, Penn, Sergey
- DVCS-CLAS trigger
third rack was installed to make cabeling easy; all racks connected to the clean power, one more power strip was ordered to use second 20A circuit
cabling between splitters and discriminators has been started in according to the Ben's map
forward carreage is in position and DVCS-CLASTRIG cable was can to the nominal length, signal is in gate about 30ns from the beginning of the gate pulse, gate cables is in production, hope to get another 20ns
EPICS readout for scalers in both CLASTRIG2 and DVCSTRIG is working, scaler histograms and corresponding MEDM GUIs to be checked; normally all scalers will be reported in Hz; all quadrons counts equally
Ben developed pattern test for the CLASTRIG2, extra v1495 board was installed in clastrig2 and connected to the main v1495, test was started from Windows GUI and passed successfully; DVCSTRIG test to be conducted - VERY IMPORTANT ! also wiil look at polarity of the optput cables
trigger downloading scripts were adjusted, downloading/uploading works fine, uploading LUT still not implemented
L2 to be tested