February 13, 2008 online meeting minutes: Difference between revisions
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We had first discussion on CLAS12 level2 trigger design which is optional for CLAS12 uograde. Sergey B. described general design for Segment Finder and Road Finder components. In according to the plan level2 will be not a pipeline system, it will start on level1 accept signal. Segment finder will process data from entire superlayer, and execution time will be constant for any number of hits. Road finder will process input segments one by one, and the maximum number of possible combinations will be set; if that number is exceeded then level2 will issue 'l2pass' signal. Dave made several useful comments, and Sergey will continue with design. | We had first discussion on CLAS12 level2 trigger design which is optional for CLAS12 uograde. Sergey B. described general design for Segment Finder and Road Finder components. In according to the plan level2 will be not a pipeline system, it will start on level1 accept signal. Segment finder will process data from entire superlayer, and execution time will be constant for any number of hits. Road finder will process input segments one by one, and the maximum number of possible combinations will be set; if that number is exceeded then level2 will issue 'l2pass' signal. Dave made several useful comments, and Sergey will continue with design. | ||
One important issue is related to the expected superlayer unefficiency: since we should be able to find the road using 5 out of 6 superlayers, region-based segment finding become not very useful so we'll not implement it on segment-finding level, although it can be taken into account somehow in road finder. | |||
We discussed several projects we want to complete during downtime. FASTBUS power supplies seems too low at +-5V current (115A), we may need to increase it to 230A, will discuss it with WIENER. Mark Jones asked to borrow 10 1877 TDCs, Sergey P. will test all boards arrieved recently and 10 boards will be provided. High Voltage 1535 boards are under testing by Sergey P. along with splitters, they will be installed in the Hall after testing. One of Lecroy mainframes in the counting house shows wierd behaviour, will be monitored closely using serial connection. Inventory database is in progress, will continue until everything is there. G9A data files with swap problem will be fixed and written to the SILO with extension *.B** (runs from 56097 to 56118). Sergey B. is planning to finish new firmware testing for v1190/v1290 TDCs - long time project. | We discussed several projects we want to complete during downtime. FASTBUS power supplies seems too low at +-5V current (115A), we may need to increase it to 230A, will discuss it with WIENER. Mark Jones asked to borrow 10 1877 TDCs, Sergey P. will test all boards arrieved recently and 10 boards will be provided. High Voltage 1535 boards are under testing by Sergey P. along with splitters, they will be installed in the Hall after testing. One of Lecroy mainframes in the counting house shows wierd behaviour, will be monitored closely using serial connection. Inventory database is in progress, will continue until everything is there. G9A data files with swap problem will be fixed and written to the SILO with extension *.B** (runs from 56097 to 56118). Sergey B. is planning to finish new firmware testing for v1190/v1290 TDCs - long time project. | ||
Revision as of 13:49, 10 March 2008
present: Sergey Boyarinov, Sergey Pozdnyakov, Dave Doughty, Hai Dong
We had first discussion on CLAS12 level2 trigger design which is optional for CLAS12 uograde. Sergey B. described general design for Segment Finder and Road Finder components. In according to the plan level2 will be not a pipeline system, it will start on level1 accept signal. Segment finder will process data from entire superlayer, and execution time will be constant for any number of hits. Road finder will process input segments one by one, and the maximum number of possible combinations will be set; if that number is exceeded then level2 will issue 'l2pass' signal. Dave made several useful comments, and Sergey will continue with design. One important issue is related to the expected superlayer unefficiency: since we should be able to find the road using 5 out of 6 superlayers, region-based segment finding become not very useful so we'll not implement it on segment-finding level, although it can be taken into account somehow in road finder.
We discussed several projects we want to complete during downtime. FASTBUS power supplies seems too low at +-5V current (115A), we may need to increase it to 230A, will discuss it with WIENER. Mark Jones asked to borrow 10 1877 TDCs, Sergey P. will test all boards arrieved recently and 10 boards will be provided. High Voltage 1535 boards are under testing by Sergey P. along with splitters, they will be installed in the Hall after testing. One of Lecroy mainframes in the counting house shows wierd behaviour, will be monitored closely using serial connection. Inventory database is in progress, will continue until everything is there. G9A data files with swap problem will be fixed and written to the SILO with extension *.B** (runs from 56097 to 56118). Sergey B. is planning to finish new firmware testing for v1190/v1290 TDCs - long time project.