CLAS12 Trigger System Design

Leader: Sergey Boyarinov

Support: David Doughty, Chris Cuevas, Ed Jastrzembski

Goal: CLAS12 Trigger System Design

Status: in progress

Project was planned in June 2006 to be completed during FY07. Actual job started in November 2006. We had several meetings discussing existing CLAS trigger, what can be improved in CLAS12 desing, and new technologies available today.

First very preliminary CLAS12 Trigger System design was presented and discussed on Friday upgrade meeting December 15, 2006 (PowerPoint, HTML).

Trigger Efficiency Studies

Trigger efficiency simulation is very important but was not started yet.

Level 1: Forward Calorimeter Cluster Finding

Currently we are trying to develop Forward Calorimeter Cluster Finding algorithm which can be used in Level 1. We started from algorithm used in data analysis, and we hope to develop similar procedure to be loaded into FPGA.

Ed's mail on FPGA-based look up tables:

 Thu, 25 Jan 2007 13:47:39 -0500 (EST)
 To: Serguei Boiarinov <boiarino@jlab.org>
 CC: Hai Dong <hdong@jlab.org>, "C. Cuevas" <cuevas@jlab.org>,
       David Abbott <abbottd@jlab.org>
 Subject: FPGA look up tables
 Hi Sergey,
   I did some investigating on the use of FPGA memory as a look up 
 table for trigger system applications.  For Altera FPGAs, the total 
 on-chip memory can be up to 9 Mbits.  However, the largest single RAM 
 block is 512 Kbits.  This can be organized as     64K x 8, 32K x 16, 16K 
 x 32, ... , or 4K x 128.  Larger chips have multiple 512 Kbit blocks 
 (along with smaller and faster blocks).  Thus, a look up table with as  
 many as 16 inputs and 8 outputs can be created.  Multiple tables can be 
 created in the larger capacity FPGAs.  The downside of using the large 
 capacity FPGAs is that the pin count and cost also increases with memory 
 capacity.  For example, 9 Mbit Altera chips have pin counts of  > 1000 
 pins (BGA) and cost ~$3000 each.
    To test the performance in an Altera FPGA, I created  the following 
 cascaded (2-level) look up table using 512 Kbit segments:   (64K x 8, 
 64K x 8) => (64K x 8).     (i.e. 32 inputs => 8 outputs).   The timing 
 analysis performed by the Altera software indicates that the design will 
 run at > 250MHz clock frequency.  This fits in a 484 pin BGA (with much 
 spare logic).
    I'll check with Hai Dong (Fast Electronics Group) about memory 
 resources in Xilinx FPGAs.  He may also be able to comment on the 
 performance of such a look up table in a Xilinx target.  It is probably 
 comparable to the Altera's speed.
      - Ed J.