VHDL programming

Basic rules for V1595-based CLAS triggers

In general VHDL files contains following sections:

1. Includes, for example:

library ieee;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
use IEEE.Std_Logic_unsigned.all;

2. Entity declaration, includes name and IO signals description

entity HallBTrigger is

port( A  : IN std_logic_vector (31 DOWNTO 0); -- In A (32 x LVDS/ECL)

               -- describe all IO signals here

);

end HallBTrigger;

3. Actual body, where component includes another entity

architecture Synthesis of HallBTrigger is

component SectorPeripheral is generic( BASE_ADDR : std_logic_vector(15 downto 8) ); port( RESET : in std_logic;

                       -- describe all IO signals here

); end component;