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CLAS12 DC (Mac 14-nov-2007): 2 stereo, +-6 degrees, good resolution (1% dp/p, 1 mrad angle), six 6-layer superlayers, 112 wires per layer; reconstruction improvements: use double hits, use segment angle in road dictionary, early l-r ambig. resolution (now it resolved locally and then corrected after track reconstructed ?), find tracks with no TOF hit and cut off accidental tracks (using residials ?), derive off-diagonal terms in error matrix | CLAS12 DC (Mac 14-nov-2007): 2 stereo, +-6 degrees, good resolution (1% dp/p, 1 mrad angle), six 6-layer superlayers, 112 wires per layer; reconstruction improvements: use double hits, use segment angle in road dictionary, early l-r ambig. resolution (now it resolved locally and then corrected after track reconstructed ?), find tracks with no TOF hit and cut off accidental tracks (using residials ?), derive off-diagonal terms in error matrix | ||
SVT readout: | |||
SVX4 - old chip | |||
132ns clock, 40pipeline cells ->5.2us trigger latency; can select readout window like pipeline TDCs (position defined +-132us, window size 132ns fixed) | |||
initial part stored upto 4 events, they are rotating internally | |||
32 bits per hit, 128 channels per chip, ... -> 3.2us per chip to get data from the chip to the buffer of 512 full events | |||
L2 pipeline 16us | |||
L1 latency from Amrit is 3us, Amrit will try to make it 4us | |||
FSSR 125ns instead of 132ns | |||
Revision as of 10:25, 14 March 2008
CLAS12 DC (Mac 14-nov-2007): 2 stereo, +-6 degrees, good resolution (1% dp/p, 1 mrad angle), six 6-layer superlayers, 112 wires per layer; reconstruction improvements: use double hits, use segment angle in road dictionary, early l-r ambig. resolution (now it resolved locally and then corrected after track reconstructed ?), find tracks with no TOF hit and cut off accidental tracks (using residials ?), derive off-diagonal terms in error matrix
SVT readout:
SVX4 - old chip 132ns clock, 40pipeline cells ->5.2us trigger latency; can select readout window like pipeline TDCs (position defined +-132us, window size 132ns fixed) initial part stored upto 4 events, they are rotating internally 32 bits per hit, 128 channels per chip, ... -> 3.2us per chip to get data from the chip to the buffer of 512 full events L2 pipeline 16us L1 latency from Amrit is 3us, Amrit will try to make it 4us
FSSR 125ns instead of 132ns