May 23, 2012 online meeting minutes: Difference between revisions
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present: Sergey Boyarinov, | present: Sergey Boyarinov, Hai Dong, Bryan Moffit, Sergey Pozdnyakov, William Gu, Ben Raydo, Scott Kaneta, Chris Cuevas | ||
1. HPS/SVT test runs experience and future electronics development | 1. HPS/SVT test runs experience and future electronics development | ||
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* after master power recycled, slave need to be recycled as well | * after master power recycled, slave need to be recycled as well | ||
* occasional TID busy condition after first few events - need to be investigated | * with new firmware: occasional TID busy condition after first few events - need to be investigated | ||
* 46kHz internal TID rate ? | |||
Future development: | Future development: | ||
* FADC: 8 bit 4 ns in trigger (need 5Gbit lines and/or 4 lines to CTP) | * FADC: report tdc as first par in pulse integration mode; 8 bit 4 ns in trigger (need 5Gbit lines and/or 4 lines to CTP); fast readiness reporting | ||
* CTP: 5GBit/4lines from FADCs, more fiber outputs to SSP, bigger FPGA, 'normal' access for event-by-event trigger information readout and firmware upgrade | * CTP: 5GBit/4lines from FADCs, more fiber outputs to SSP, bigger FPGA, 'normal' access for event-by-event trigger information readout and firmware upgrade | ||
Latest revision as of 10:58, 23 May 2012
present: Sergey Boyarinov, Hai Dong, Bryan Moffit, Sergey Pozdnyakov, William Gu, Ben Raydo, Scott Kaneta, Chris Cuevas
1. HPS/SVT test runs experience and future electronics development
HPS test run was a big success for the new electronics and daq software testing. 2 VXS crates with 14 FADCs each worked for several weeks without major problems. 2 CTPs and 1 SSP boards formed calorimeter-based trigger searching for single and pair clusters, worked fine as well. Although event rate was limited because of beam conditions (photon beam only, no electron beam was delivered as we planed), third slac svt crate and old event builder, front end worked as planed and we are confident to meet 12GeV requirements.
In addition CLAS SVT test run was conducted during last week of running using new VXS readout boards, and it worked as planed as well.
List of features implemented for HPS run:
- pulse integration was implemented into FADC trigger chain, integration was conducted above preloaded pedestals and using preloaded above-pedestal-thresholds; FADCs reported 5 bits od ADC integral and 3 bits of timing, allowing 4ns-clock triggering in following CTP and SSP boards (Hai)
- CTP-based cluster finding algorithm was implemented (Scott)
- SSP-based trigger was implemented, along with ROOT-based trigger control GUIs, event-by-event trigger information readout (Ben)
Problems observed:
- big timing shift between different TID boards firmwares - fixed during the run
- occasional resync between master and slave TIDs, affects both trigger and readout functionality - software patch was applied by Bryan and Gu, new firmware was improved, more studies will be conducted
- after master power recycled, slave need to be recycled as well
- with new firmware: occasional TID busy condition after first few events - need to be investigated
- 46kHz internal TID rate ?
Future development:
- FADC: report tdc as first par in pulse integration mode; 8 bit 4 ns in trigger (need 5Gbit lines and/or 4 lines to CTP); fast readiness reporting
- CTP: 5GBit/4lines from FADCs, more fiber outputs to SSP, bigger FPGA, 'normal' access for event-by-event trigger information readout and firmware upgrade
More development needed:
- VSCM board (SVT readout)
- DCRB board, include daughter board extension possibility (for ADC) (Drift Chamber readout)