VHDL programming

Basic rules for V1495-based CLAS triggers

In general VHDL files contains following sections:

1. Includes, for example:

library ieee;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
use IEEE.Std_Logic_unsigned.all;

2. Entity declaration, includes name and IO signals description

entity HallBTrigger is
        port(
               A        : IN     std_logic_vector (31 DOWNTO 0);  -- In A (32 x LVDS/ECL)
               -- describe all IO signals here
       );
end HallBTrigger;

3. Actual body beginning:

architecture Synthesis of HallBTrigger is

4. Description of another entity (just describes, actual include will be done below)

       component SectorPeripheral is
               generic(
			BASE_ADDR	: std_logic_vector(15 downto 8)
		);
		port(
			RESET			: in std_logic;
                       -- describe all IO signals here
		);
	end component;

5. Internal signals, types, constnts description (internal for this entity):

	signal PLLCLK			: std_logic;
	signal HEART_BEAT_CNT	: std_logic_vector(25 downto 0) := "00000000000000000000000000";
	signal USER_DIN			: std_logic_vector(31 downto 0);
	constant NUM_USER_BUS	: integer := 21;
	type UserBusArray is array(0 to NUM_USER_BUS-1) of std_logic_vector(31 downto 0);
	signal USER_DOUT_MUXIN	: UserBusArray;

6. Begin statement and ??initial signals settings??

begin
 	nLEDG <= not HEART_BEAT_CNT(25);
	nLEDR <= PLL_LOCK;
	SYS_RESET <= not nLBRES;

7. Process(es) declarations; processes are executed if one of the signals in parameter's list was changed (in this example it is LCLK)

	process(LCLK)
	begin
		if rising_edge(LCLK) then
			HEART_BEAT_CNT <= HEART_BEAT_CNT + 1;
		end if;
	end process;

8. Actual mapping for components described above. Multiple copies of the same component can be created (6 in our example). In port map section, signals on the left are component IO signal names as they appeares in the component definition, and signals on the right are local signals or port signals. Index I is used in mapping to connect different copies of the component the desired way.

	SectorLogicGen: for I in 0 to 5 generate
		SectorPeripheral_SectorN: SectorPeripheral
			generic map(
				BASE_ADDR		=> x"10" + conv_std_logic_vector(I, 8)
			)
			port map(
				RESET			=> SYS_RESET,
				ENABLE_SCALERS          => ENABLE_SCALERS,
				LCLK			=> LCLK,
				ADDR			=> USER_ADDR,
  				DIN			=> USER_DIN,
				DOUT			=> USER_DOUT_MUXIN(I),
                             -- and so on
			);
	end generate;

9. Last statement:

end Synthesis;