September 30, 2009 online meeting minutes: Difference between revisions
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present: Sergey Boyarinov S.P., Ben | present: Sergey Boyarinov, S.P., Ben | ||
1. Discr: | 1. Discr: | ||
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* investigate spikes in trigger output distributions (change input frequency etc) | * investigate spikes in trigger output distributions (change input frequency etc) | ||
* threshold dependence is very linear for one channel, need to check channel-to-channel dependence, typical must be +-1mv (spec has +-3mv max) | * threshold dependence is very linear for one channel, need to check channel-to-channel dependence, typical must be +-1mv (spec has +-3mv max); slope measured as 0.263, must be 0.25 (maybe scope is not calibrated good enough, Ben will check) | ||
* | * tdc output pulse width: need to have a calibration on board level to make sure it starts from zero and linear | ||
* trg output width will have 4ns step | |||
* delay for trg is 75-80ns, need as low as possible, will be 15ns in new revision with 4ns step | |||
* OR output works, masks works | |||
* test input to be implemented | |||
* scalers (ungated and gated) to be tested, they resets on read; readout will be the same as JLAB FADCs (DMA readout); gated and ungated scalers must to be latched together - to be implemented | |||
* temperature dependence test to be completed, probably by changing fan speed in VME crate | |||
2. eg6 run | |||
* BONUS electronics: assembling in Hall B under way, will try to make something working tonight; a lot of work to commission electronics and software ... | |||
Latest revision as of 11:02, 30 September 2009
present: Sergey Boyarinov, S.P., Ben
1. Discr:
- compensate for propagation if possible
- test with different TDC boards and low amplitude pulse, probably triangle shape
- investigate spikes in trigger output distributions (change input frequency etc)
- threshold dependence is very linear for one channel, need to check channel-to-channel dependence, typical must be +-1mv (spec has +-3mv max); slope measured as 0.263, must be 0.25 (maybe scope is not calibrated good enough, Ben will check)
- tdc output pulse width: need to have a calibration on board level to make sure it starts from zero and linear
- trg output width will have 4ns step
- delay for trg is 75-80ns, need as low as possible, will be 15ns in new revision with 4ns step
- OR output works, masks works
- test input to be implemented
- scalers (ungated and gated) to be tested, they resets on read; readout will be the same as JLAB FADCs (DMA readout); gated and ungated scalers must to be latched together - to be implemented
- temperature dependence test to be completed, probably by changing fan speed in VME crate
2. eg6 run
- BONUS electronics: assembling in Hall B under way, will try to make something working tonight; a lot of work to commission electronics and software ...