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During G12 run preparations on spring 2008 we decided to upgrade photon part of CLAS Level1 trigger system using CAEN v1495 logic unit. Eventually those efforts resulted in full Level1 system replacement: 6 level1 router boards and event processor board were replaced with one single v1495 unit equipped with 2 extra daughter modules. Trigger was commissioned during first phase of G12 run, last significant change was applied April 20, 2008. Most of the job was completed by Ben Raydo from Fast Electronics group. Valery Kubarovsky and Pawel Nadel-Turonski made generic trigger design and conducted trigger testing. Sergey Boyarinov, Ivan Bedlinskiy, Nerses Gevorgyan and Hovanes Egiyan integrated new hardware and software components into CLAS online and slow control systems. Technical assistance was provided by Fast Electronic Group and CODA Group personal. Current document contains basic information about the system. | During G12 run preparations on spring 2008 we decided to upgrade photon part of CLAS Level1 trigger system using CAEN v1495 logic unit. Eventually those efforts resulted in full Level1 system replacement: 6 level1 router boards and event processor board were replaced with one single v1495 unit equipped with 2 extra daughter modules. Trigger was commissioned during first phase of G12 run, last significant change was applied April 20, 2008. Most of the job was completed by Ben Raydo from Fast Electronics group. Valery Kubarovsky and Pawel Nadel-Turonski made generic trigger design and conducted trigger testing. Sergey Boyarinov, Ivan Bedlinskiy, Nerses Gevorgyan and Hovanes Egiyan integrated new hardware and software components into CLAS online and slow control systems. Technical assistance was provided by Fast Electronic Group and CODA Group personal. Current document contains basic information about the system. | ||
* general layout | * [https://clonwiki0.jlab.org/wiki/clondocs/V1495CLASTrigger/V1495largekit.jpg boards pictures], [https://clonwiki0.jlab.org/wiki/clondocs/V1495CLASTrigger/layout.jpg general layout] | ||
* v1495-based logic | * v1495-based logic: see GUI snapshots below; total propagation time is about 75ns, similar to old Level1 system | ||
* Windows-based control GUI (see [https:// | * Windows-based control GUI (see [https://clonwiki0.jlab.org/wiki/clondocs/V1495CLASTrigger/trig_gui_1.jpg snapshot1], [https://clonwiki0.jlab.org/wiki/clondocs/V1495CLASTrigger/trig_gui_2.jpg snapshot2] and [https://clonwiki0.jlab.org/wiki/clondocs/V1495CLASTrigger/trig_gui_3.jpg snapshot3]) were developed by Ben Raydo; it displays basic trigger logic and allows user to control and monitor various parts of the system using controlled logic elements, delays and lookup tables; built-in scalers are providing useful information about system functionality; system includes an multi-channel logic analyzer which was extremely useful to set appropriate delays (see [https://clonwiki0.jlab.org/wiki/clondocs/V1495CLASTrigger/trig_display_1.jpg snapshot1], [https://clonwiki0.jlab.org/wiki/clondocs/V1495CLASTrigger/trig_display_2.jpg snapshot2], [https://clonwiki0.jlab.org/wiki/clondocs/V1495CLASTrigger/trig_display_3.jpg snapshot3] and [https://clonwiki0.jlab.org/wiki/clondocs/V1495CLASTrigger/trig_display_4.jpg snapshot4]) | ||
* system incorporation into CLAS Online and Slow control: 9 OR modules were installed in sc2 crate, controlling script was provided to set appropriate masks into those units; v1495 was installed into clastrig2 trigger supervisor crate, and tcp server was developed and started under vxWorks to provide communication with Windows GUI and any other control and monitoring software running on UNIX machines; vxWorks timer-driven process is reading and reseting v1495 scalers every second placing data into semaphore-protected memory, so EPICS-related functions can extract necessary information from there; to provide EPICS support EPICS IOC was lunched along with CODA in clastrig2 crate, both systems are running together without problems; EPICS GUIs were | * system incorporation into CLAS Online and Slow control: 9 OR modules were installed in sc2 crate, controlling script was provided to set appropriate masks into those units; v1495 was installed into clastrig2 trigger supervisor crate, and tcp server was developed and started under vxWorks to provide communication with Windows GUI and any other control and monitoring software running on UNIX machines; vxWorks timer-driven process is reading and reseting v1495 scalers every second placing data into semaphore-protected memory, so EPICS-related functions can extract necessary information from there; to provide EPICS support EPICS IOC was lunched along with CODA in clastrig2 crate, both systems are running together without problems (clastrig2 'i' command [https://clonwiki0.jlab.org/wiki/clondocs/V1495CLASTrigger/clastrig2_i.txt snapshot]); EPICS GUIs were developed (see [https://clonwiki0.jlab.org/wiki/clondocs/V1495CLASTrigger/ts_bits.png snapshot1] and [https://clonwiki0.jlab.org/wiki/clondocs/V1495CLASTrigger/ts_st_view.png snapshot2]) to display trigger system scalers; Windows-based GUI was installed on clonwin2 desktop which was accessed using remote desktop software from clon04 Linux machine | ||
'''March 2010 new photon version''' | |||
Contains new Level2-related features and some small changes. Ben's email: | |||
Hi Sergey, | |||
See the attachments for the new module revision. The main changes have been | |||
switching over the a 32bit VME interface, which made the firmware a bit easier to | |||
write/compile and should simplify your 32bit scalar readout. This module will only | |||
support 32bit VME transcactions (not 16bit). | |||
Take a look at the attached TCP/VME server - I've mainly added 32bit vme messages. | |||
If you use this file you'll need to add your controls for when EPICS is actively | |||
reading out scalars (redirect the scalar address range to read from EPICS instead of | |||
the VME module, but when EPICS isn't active allow the VME commands to read directly | |||
from the module - be sure to include the scalar control register!). | |||
I've got the GUI ready to go and the VME firmware is just about ready (just needs to | |||
finish compiling) if you want to test soon (probably tomorrow is best still). | |||
Ben | |||
Manual: [https://clonwiki0.jlab.org/wiki/clondocs/Docs/HallBTriggerMarch2010_Description.pdf pdf]. | |||
'''Some notes''' | |||
'''CAEN1495 LUTs, photon version''' | |||
* L1 ECP LUT has 6 STOF inputs and 6 ECP inputs, and one output. To generate lookup table program ''level1lookupmaker'' must be used. It will take config file name WITHOUT extension assuming extension ''trg'', and will generate file with the same name and extension ''lut'' in current directory. Config file should has one line with logical equation using STOF1..STOF6 and ECP1..ECP6 names for 12 inputs. Logical AND represented by 'x' and logical OR - by '||', for example: | |||
ECP1xSTOF2||ECP1xSTOF3||STOF1xSTOF4|| | |||
'''NOTE:''' line must be ended by ||. | |||
* L1 ECC LUT works the same way, if ECP replaced by ECC, for example: | |||
ECC1xSTOF2||ECC1xSTOF3||STOF1xSTOF4|| | |||
* L2 TRG LUT has 12 inputs from 12 trigger bits, and 4 outputs connected to the level2 MLU board. To generate lookup table program ''level2lookupmaker'' must be used. It will take config file name WITHOUT extension assuming extension ''trg'', and will generate file with the same name and extension ''lut'' in current directory. Config file should contains 4 lines with logical equations, representing desired results on each of 4 output lines, for example: | |||
TRG11xTRG12||TRG3xTRG4|| | |||
TRG1xTRG2|| | |||
TRG4|| | |||
TRG8|| | |||
'''NOTE:''' it is possible that more then one output will have a signal for the particular event, it must be taken into account programming level2 mlu board. | |||
* L2 SEC LUT represents 8 possible combinations of 3 detectors: STOF, ECP and ECC. Config files tag is TS_L2_SECLOGIC following by the number representing LUT contents. If one of those detectors must be used alone, corresponding vertical column must be converted to decimal number and used in config file. If OR or AND logic must be implemented, corresponding operation must be performed in every of 8 lines, and resulting column converted to the decimal number as well. Following diagram explains how it works: | |||
ECC ECP STOF | ECC|ECP ECC|STOF ECP|STOF ECC|ECP|STOF ECC&ECP ECC&STOF ECP&STOF ECC&ECP&STOF | |||
bit00 0 0 0 | 0 0 0 0 0 0 0 0 | |||
0 0 1 | 0 1 1 1 0 0 0 0 | |||
0 1 0 | 1 0 1 1 0 0 0 0 | |||
0 1 1 | 1 1 1 1 0 0 1 0 | |||
1 0 0 | 1 1 0 1 0 0 0 0 | |||
1 0 1 | 1 1 1 1 0 1 0 0 | |||
1 1 0 | 1 1 1 1 1 0 0 0 | |||
bit07 1 1 1 | 1 1 1 1 1 1 1 1 | |||
hex: 0xF0 0xCC 0xAA | 0xFC 0xFA 0xEE 0xFE 0xC0 0xA0 0x88 0x80 | |||
dec: 240 204 170 252 250 238 254 192 160 136 128 <--- to be used in config file | |||
'''NOTE:''' since Nov 2010 it was changed as following: | |||
ECC ECP STOF3 STOF2 STOF1 | | |||
bit00 0 0 0 0 0 | | |||
0 0 0 0 1 | | |||
0 0 0 1 0 | | |||
0 0 0 1 1 | | |||
0 0 1 0 0 | | |||
0 0 1 0 1 | | |||
0 0 1 1 0 | | |||
0 0 1 1 1 | | |||
0 1 0 0 0 | | |||
0 1 0 0 1 | | |||
0 1 0 1 0 | | |||
0 1 0 1 1 | | |||
0 1 1 0 0 | | |||
0 1 1 0 1 | | |||
0 1 1 1 0 | | |||
0 1 1 1 1 | | |||
1 0 0 0 0 | | |||
1 0 0 0 1 | | |||
1 0 0 1 0 | | |||
1 0 0 1 1 | | |||
1 0 1 0 0 | | |||
1 0 1 0 1 | | |||
1 0 1 1 0 | | |||
1 0 1 1 1 | | |||
1 1 0 0 0 | | |||
1 1 0 0 1 | | |||
1 1 0 1 0 | | |||
1 1 0 1 1 | | |||
1 1 1 0 0 | | |||
1 1 1 0 1 | | |||
1 1 1 1 0 | | |||
bit31 1 1 1 1 1 | | |||
hex: 0xFFFF0000 0xFF00FF00 0xF0F0F0F0 0xCCCCCCCC 0xAAAAAAAA | | |||
'''Level2 MLU board''' | |||
L2 MLU VME board has 16 inputs: 4 from L2 TRG LUT described above, 6 from L2 SEC LUT described above, and 6 from Drift Chamber level2 logic. | |||
To load MLU VxWorks function ''level2MLUSetup()'' must be used. It will take config file name with absolute pass as an argument, generate lookup table and load it into the board. It does not currently produce any result in file. Config file must contains 16 lines, one for each combination of the 4 outputs from L2 TRG LUT, using key words PASS, FAIL and logical equations, for example: | |||
FAIL | |||
L1S1xL2S1||L1S2xL2S2||L1S3xL2S3||L1S4xL2S4||L1S5xL2S5||L1S6xL2S6|| | |||
L1S1xL2S1||L1S2xL2S2||L1S3xL2S3||L1S4xL2S4||L1S5xL2S5||L1S6xL2S6|| | |||
FAIL | |||
L1S1xL2S1||L1S2xL2S2||L1S3xL2S3||L1S4xL2S4||L1S5xL2S5||L1S6xL2S6|| | |||
FAIL | |||
FAIL | |||
FAIL | |||
L1S1xL2S1||L1S2xL2S2||L1S3xL2S3||L1S4xL2S4||L1S5xL2S5||L1S6xL2S6|| | |||
FAIL | |||
FAIL | |||
FAIL | |||
FAIL | |||
FAIL | |||
FAIL | |||
FAIL | |||
'''NOTE:''' example above contains logical equations in lines 1,2,4 and 8 (counting from 0) which corresponds to the binary code on the 4 outputs from L2 TRG LUT connected to the 4 inputs of L2 MLU. If any combinations of those 4 signals are expected, then other lines in config file must be filled in as well, for example if inputs 1 and 2 can be fired at the same time, code 3 will be presented and line number 3 in config file must describe what logic will be executed in such case | |||
Latest revision as of 15:06, 17 April 2015
During G12 run preparations on spring 2008 we decided to upgrade photon part of CLAS Level1 trigger system using CAEN v1495 logic unit. Eventually those efforts resulted in full Level1 system replacement: 6 level1 router boards and event processor board were replaced with one single v1495 unit equipped with 2 extra daughter modules. Trigger was commissioned during first phase of G12 run, last significant change was applied April 20, 2008. Most of the job was completed by Ben Raydo from Fast Electronics group. Valery Kubarovsky and Pawel Nadel-Turonski made generic trigger design and conducted trigger testing. Sergey Boyarinov, Ivan Bedlinskiy, Nerses Gevorgyan and Hovanes Egiyan integrated new hardware and software components into CLAS online and slow control systems. Technical assistance was provided by Fast Electronic Group and CODA Group personal. Current document contains basic information about the system.
- v1495-based logic: see GUI snapshots below; total propagation time is about 75ns, similar to old Level1 system
- Windows-based control GUI (see snapshot1, snapshot2 and snapshot3) were developed by Ben Raydo; it displays basic trigger logic and allows user to control and monitor various parts of the system using controlled logic elements, delays and lookup tables; built-in scalers are providing useful information about system functionality; system includes an multi-channel logic analyzer which was extremely useful to set appropriate delays (see snapshot1, snapshot2, snapshot3 and snapshot4)
- system incorporation into CLAS Online and Slow control: 9 OR modules were installed in sc2 crate, controlling script was provided to set appropriate masks into those units; v1495 was installed into clastrig2 trigger supervisor crate, and tcp server was developed and started under vxWorks to provide communication with Windows GUI and any other control and monitoring software running on UNIX machines; vxWorks timer-driven process is reading and reseting v1495 scalers every second placing data into semaphore-protected memory, so EPICS-related functions can extract necessary information from there; to provide EPICS support EPICS IOC was lunched along with CODA in clastrig2 crate, both systems are running together without problems (clastrig2 'i' command snapshot); EPICS GUIs were developed (see snapshot1 and snapshot2) to display trigger system scalers; Windows-based GUI was installed on clonwin2 desktop which was accessed using remote desktop software from clon04 Linux machine
March 2010 new photon version
Contains new Level2-related features and some small changes. Ben's email:
Hi Sergey, See the attachments for the new module revision. The main changes have been switching over the a 32bit VME interface, which made the firmware a bit easier to write/compile and should simplify your 32bit scalar readout. This module will only support 32bit VME transcactions (not 16bit). Take a look at the attached TCP/VME server - I've mainly added 32bit vme messages. If you use this file you'll need to add your controls for when EPICS is actively reading out scalars (redirect the scalar address range to read from EPICS instead of the VME module, but when EPICS isn't active allow the VME commands to read directly from the module - be sure to include the scalar control register!). I've got the GUI ready to go and the VME firmware is just about ready (just needs to finish compiling) if you want to test soon (probably tomorrow is best still). Ben
Manual: pdf.
Some notes
CAEN1495 LUTs, photon version
- L1 ECP LUT has 6 STOF inputs and 6 ECP inputs, and one output. To generate lookup table program level1lookupmaker must be used. It will take config file name WITHOUT extension assuming extension trg, and will generate file with the same name and extension lut in current directory. Config file should has one line with logical equation using STOF1..STOF6 and ECP1..ECP6 names for 12 inputs. Logical AND represented by 'x' and logical OR - by '||', for example:
ECP1xSTOF2||ECP1xSTOF3||STOF1xSTOF4||
NOTE: line must be ended by ||.
- L1 ECC LUT works the same way, if ECP replaced by ECC, for example:
ECC1xSTOF2||ECC1xSTOF3||STOF1xSTOF4||
- L2 TRG LUT has 12 inputs from 12 trigger bits, and 4 outputs connected to the level2 MLU board. To generate lookup table program level2lookupmaker must be used. It will take config file name WITHOUT extension assuming extension trg, and will generate file with the same name and extension lut in current directory. Config file should contains 4 lines with logical equations, representing desired results on each of 4 output lines, for example:
TRG11xTRG12||TRG3xTRG4|| TRG1xTRG2|| TRG4|| TRG8||
NOTE: it is possible that more then one output will have a signal for the particular event, it must be taken into account programming level2 mlu board.
- L2 SEC LUT represents 8 possible combinations of 3 detectors: STOF, ECP and ECC. Config files tag is TS_L2_SECLOGIC following by the number representing LUT contents. If one of those detectors must be used alone, corresponding vertical column must be converted to decimal number and used in config file. If OR or AND logic must be implemented, corresponding operation must be performed in every of 8 lines, and resulting column converted to the decimal number as well. Following diagram explains how it works:
ECC ECP STOF | ECC|ECP ECC|STOF ECP|STOF ECC|ECP|STOF ECC&ECP ECC&STOF ECP&STOF ECC&ECP&STOF
bit00 0 0 0 | 0 0 0 0 0 0 0 0
0 0 1 | 0 1 1 1 0 0 0 0
0 1 0 | 1 0 1 1 0 0 0 0
0 1 1 | 1 1 1 1 0 0 1 0
1 0 0 | 1 1 0 1 0 0 0 0
1 0 1 | 1 1 1 1 0 1 0 0
1 1 0 | 1 1 1 1 1 0 0 0
bit07 1 1 1 | 1 1 1 1 1 1 1 1
hex: 0xF0 0xCC 0xAA | 0xFC 0xFA 0xEE 0xFE 0xC0 0xA0 0x88 0x80
dec: 240 204 170 252 250 238 254 192 160 136 128 <--- to be used in config file
NOTE: since Nov 2010 it was changed as following:
ECC ECP STOF3 STOF2 STOF1 |
bit00 0 0 0 0 0 |
0 0 0 0 1 |
0 0 0 1 0 |
0 0 0 1 1 |
0 0 1 0 0 |
0 0 1 0 1 |
0 0 1 1 0 |
0 0 1 1 1 |
0 1 0 0 0 |
0 1 0 0 1 |
0 1 0 1 0 |
0 1 0 1 1 |
0 1 1 0 0 |
0 1 1 0 1 |
0 1 1 1 0 |
0 1 1 1 1 |
1 0 0 0 0 |
1 0 0 0 1 |
1 0 0 1 0 |
1 0 0 1 1 |
1 0 1 0 0 |
1 0 1 0 1 |
1 0 1 1 0 |
1 0 1 1 1 |
1 1 0 0 0 |
1 1 0 0 1 |
1 1 0 1 0 |
1 1 0 1 1 |
1 1 1 0 0 |
1 1 1 0 1 |
1 1 1 1 0 |
bit31 1 1 1 1 1 |
hex: 0xFFFF0000 0xFF00FF00 0xF0F0F0F0 0xCCCCCCCC 0xAAAAAAAA |
Level2 MLU board
L2 MLU VME board has 16 inputs: 4 from L2 TRG LUT described above, 6 from L2 SEC LUT described above, and 6 from Drift Chamber level2 logic. To load MLU VxWorks function level2MLUSetup() must be used. It will take config file name with absolute pass as an argument, generate lookup table and load it into the board. It does not currently produce any result in file. Config file must contains 16 lines, one for each combination of the 4 outputs from L2 TRG LUT, using key words PASS, FAIL and logical equations, for example:
FAIL L1S1xL2S1||L1S2xL2S2||L1S3xL2S3||L1S4xL2S4||L1S5xL2S5||L1S6xL2S6|| L1S1xL2S1||L1S2xL2S2||L1S3xL2S3||L1S4xL2S4||L1S5xL2S5||L1S6xL2S6|| FAIL L1S1xL2S1||L1S2xL2S2||L1S3xL2S3||L1S4xL2S4||L1S5xL2S5||L1S6xL2S6|| FAIL FAIL FAIL L1S1xL2S1||L1S2xL2S2||L1S3xL2S3||L1S4xL2S4||L1S5xL2S5||L1S6xL2S6|| FAIL FAIL FAIL FAIL FAIL FAIL FAIL
NOTE: example above contains logical equations in lines 1,2,4 and 8 (counting from 0) which corresponds to the binary code on the 4 outputs from L2 TRG LUT connected to the 4 inputs of L2 MLU. If any combinations of those 4 signals are expected, then other lines in config file must be filled in as well, for example if inputs 1 and 2 can be fired at the same time, code 3 will be presented and line number 3 in config file must describe what logic will be executed in such case