Vivado

vitis

Project / Project Settings / Synthesis Settings

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Solution settings / Synthesis Settings

clock period: 8, clock uncertainty: 3.0
part selection: xc7vx550tffg1158-1
flow target: Vivado IP Flow Target

Migration from Vivado

in ecal.cc:
#pragma HLS PIPELINE II=4   ->   #pragma HLS DATAFLOW

everywhere:
#pragma HLS INTERFACE ap_stable port=threshold   ->   #pragma HLS stable variable=threshold
#pragma HLS DATA_PACK variable=s_coord2          ->   #pragma HLS aggregate variable=s_coord2 compact=bit
#pragma HLS INLINE                               ->   remove if used together with PIPELINE
#pragma HLS PIPELINE II=1 enable_flush           ->   #pragma HLS PIPELINE II=1 style=flp

vivado on clondaq6

git clone https://github.com/JeffersonLab/fe_fw.git

old stuff

.cshrc must contains following:

if ( ($HOST == "braydopc2") || ($HOST == "braydopc2.jlab.org") ) then
  source /opt/Xilinx/Vivado/2015.4/settings64.csh 
endif

ssh boiarino@braydopc2

cd vivado

vivado_hls