August 3, 2016 online meeting minutes: Difference between revisions
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Created page with "present: Sergey Boyarinov, Cole Smith, Ben Raydo VTP status was discussed: * testing: VTP board assembling almost done, front panels being delivered and installed, acceptanc..." |
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present: Sergey Boyarinov, Cole Smith, Ben Raydo | present: Sergey Boyarinov, Cole Smith, Ben Raydo (and Sergey talked to Bryan Moffit next day about Linux porting, plan included here) | ||
VTP status was discussed: | VTP status was discussed: | ||
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* testing: VTP board assembling almost done, front panels being delivered and installed, acceptance tests will start today and finished as soon as all front panels delivered (about week, unless problems found); several modules should be available for installation in a week; will install in EC and implement inner only for the beginning (sector 2); will be triggering from PCAL's v1495 and read VTP as ROC, then later take trigger from VTP itself; visualization, configuration software to be developed (some exist but have to be adjusted for VTP) | * testing: VTP board assembling almost done, front panels being delivered and installed, acceptance tests will start today and finished as soon as all front panels delivered (about week, unless problems found); several modules should be available for installation in a week; will install in EC and implement inner only for the beginning (sector 2); will be triggering from PCAL's v1495 and read VTP as ROC, then later take trigger from VTP itself; visualization, configuration software to be developed (some exist but have to be adjusted for VTP) | ||
* Linux porting: | * Linux porting: Bryan is working on it, have some problems related to new 'System V' startup procedures, hope to resolve it soon | ||
* CODA porting: | * CODA porting: coda_roc component was ported on ARM processor for HPS already so do not expect surprises; big fpga registers are mapped to arm space so communication should be simple; data will be streamed from big fpga to arm and send out using arm's 1GBit ethernet port, in future will use big fpga ports directly | ||
* ECAL implementation: | * ECAL implementation: work continue; we discussed some details including visualization needed for development | ||
* installation schedule: | * installation schedule: as soon as acceptance test passed, first board will go to the forward carriage so we can start porting it into daq | ||
* etc: TS and TD boards support was added to the CLAS12 DAQ, configuration with 37 crates (trig1 with TS and TDs and 36 forward carriage crates) was tested using random pulser, average data rate reaches 1.35GBit/sec; cables being installed to make OR trigger using CAEN v1495 boards installed in 6 sectors, so DAQ is ready for VTP installation | * etc: TS and TD boards support was added to the CLAS12 DAQ, configuration with 37 crates (trig1 with TS and TDs and 36 forward carriage crates) was tested using random pulser, average data rate reaches 1.35GBit/sec; cables being installed to make OR trigger using CAEN v1495 boards installed in 6 sectors, so DAQ is ready for VTP installation | ||
Latest revision as of 06:28, 5 August 2016
present: Sergey Boyarinov, Cole Smith, Ben Raydo (and Sergey talked to Bryan Moffit next day about Linux porting, plan included here)
VTP status was discussed:
- testing: VTP board assembling almost done, front panels being delivered and installed, acceptance tests will start today and finished as soon as all front panels delivered (about week, unless problems found); several modules should be available for installation in a week; will install in EC and implement inner only for the beginning (sector 2); will be triggering from PCAL's v1495 and read VTP as ROC, then later take trigger from VTP itself; visualization, configuration software to be developed (some exist but have to be adjusted for VTP)
- Linux porting: Bryan is working on it, have some problems related to new 'System V' startup procedures, hope to resolve it soon
- CODA porting: coda_roc component was ported on ARM processor for HPS already so do not expect surprises; big fpga registers are mapped to arm space so communication should be simple; data will be streamed from big fpga to arm and send out using arm's 1GBit ethernet port, in future will use big fpga ports directly
- ECAL implementation: work continue; we discussed some details including visualization needed for development
- installation schedule: as soon as acceptance test passed, first board will go to the forward carriage so we can start porting it into daq
- etc: TS and TD boards support was added to the CLAS12 DAQ, configuration with 37 crates (trig1 with TS and TDs and 36 forward carriage crates) was tested using random pulser, average data rate reaches 1.35GBit/sec; cables being installed to make OR trigger using CAEN v1495 boards installed in 6 sectors, so DAQ is ready for VTP installation