February 25, 2009 online meeting minutes: Difference between revisions
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present: Sergey Boyarinov | present: Sergey Boyarinov, Sergey Pozdnyakov, Nerses Gevorgyan, Ben Raydo, Chris Cuevas | ||
1. JLAB | 1. JLAB discriminator | ||
+ range 0-1V, accuracy is +-3mV, step 0.25mV; there is temperature dependence - to be documented | |||
* | * + preamplifiers will stay but gain reduced to 2 from 4; gain can be changed by changing resistors (soldered) | ||
* | * + positive pulse will not harm | ||
* individual | * + mask outputs: can disable all, enable all, disable trigger outputs only (cannot disable tdc output only), all individual channels | ||
* add | * + add test input: directly to digital side | ||
* | * + individual channel thresholds, min 10 mV - real: will try to satisfy (histeresis is set t0 5mV, so 10mVthreshold is on the edge) | ||
* | * + add second output connector: yes, 2 34-pin | ||
* | * + different thresholds for output 1 and output 2 (optional on the board) | ||
* | * + individual programmable width for trigger, step 4ns, min 4ns; for tdc output is common, 10ns min, at least 4ns step; max=100ns; non-updating mode | ||
* | * + channel-based output delays for trigger output connector - about 20ns constant part, plus 4ns step (remember jitter 4ns !), 512ns max | ||
* | * + 16-channel board !!! | ||
* | * + fast enough: 100MHz (double pulse res 11ns) | ||
* | * + internal delay (trigger is 20ns, tdc is less then 10ns) | ||
* | * + thermodrift - to be studied on prototype | ||
* | * + remove monitor | ||
* | * + not-stop scaler readout | ||
* VME readout: write/read all registers, A32/D64 with DMA | * + 2 set of 32-bit scalers, one of then has external gate | ||
* + OR for trigger output, same time as signal on trigger output connector (NIM) | |||
* + user code in FPGA (left-right compensation, etc) - will not implement anything but will be a space in main FPGA chip | |||
* + VME readout: write/read all registers, A32/D64 with DMA | |||
* + VME firmware upgrade | |||
2. eg1dvcs run status | |||
* BASEB must be modified (symb likns, top make file etc), maybe redirect epics's make application to our BASEB - Nerses | |||
* ECHV1 boards sometimes trips, we believe that it is related to bad connectors; trying to push pins in | |||
* Sergey B. is working to implement recovery procedure to have in DB runs with failed end | |||
* SUN intel-based clon01 arrived, will be commission; XRT graph license connected to existing machine, need to be resolved | |||
* automount problem with silo staging area, will be reported to CC | |||
Latest revision as of 12:00, 25 February 2009
present: Sergey Boyarinov, Sergey Pozdnyakov, Nerses Gevorgyan, Ben Raydo, Chris Cuevas
1. JLAB discriminator
+ range 0-1V, accuracy is +-3mV, step 0.25mV; there is temperature dependence - to be documented
- + preamplifiers will stay but gain reduced to 2 from 4; gain can be changed by changing resistors (soldered)
- + positive pulse will not harm
- + mask outputs: can disable all, enable all, disable trigger outputs only (cannot disable tdc output only), all individual channels
- + add test input: directly to digital side
- + individual channel thresholds, min 10 mV - real: will try to satisfy (histeresis is set t0 5mV, so 10mVthreshold is on the edge)
- + add second output connector: yes, 2 34-pin
- + different thresholds for output 1 and output 2 (optional on the board)
- + individual programmable width for trigger, step 4ns, min 4ns; for tdc output is common, 10ns min, at least 4ns step; max=100ns; non-updating mode
- + channel-based output delays for trigger output connector - about 20ns constant part, plus 4ns step (remember jitter 4ns !), 512ns max
- + 16-channel board !!!
- + fast enough: 100MHz (double pulse res 11ns)
- + internal delay (trigger is 20ns, tdc is less then 10ns)
- + thermodrift - to be studied on prototype
- + remove monitor
- + not-stop scaler readout
- + 2 set of 32-bit scalers, one of then has external gate
- + OR for trigger output, same time as signal on trigger output connector (NIM)
- + user code in FPGA (left-right compensation, etc) - will not implement anything but will be a space in main FPGA chip
- + VME readout: write/read all registers, A32/D64 with DMA
- + VME firmware upgrade
2. eg1dvcs run status
- BASEB must be modified (symb likns, top make file etc), maybe redirect epics's make application to our BASEB - Nerses
- ECHV1 boards sometimes trips, we believe that it is related to bad connectors; trying to push pins in
- Sergey B. is working to implement recovery procedure to have in DB runs with failed end
- SUN intel-based clon01 arrived, will be commission; XRT graph license connected to existing machine, need to be resolved
- automount problem with silo staging area, will be reported to CC