September 17, 2008 online meeting minutes: Difference between revisions
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present: Sergey Boyarinov, Valery Kubarovsky, Sergey Pozdnyakov, | present: Sergey Boyarinov, Valery Kubarovsky, Chris Cuevas, Ben Raydo, Sergey Pozdnyakov, Pawel Nadel-Turonski | ||
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racks will be in final destination today | racks will be in final destination today | ||
all discriminators have test inputs connected ( 6 groups 5-6 boards each), signals looks fine | |||
all discriminators have test inputs connected ( 6 groups 5-6 boards each), signals looks fine; width must be more then 25ns, otherwise built-in scalers can miss them (40ns will be fine) | |||
one pulser (from FC) | |||
measure cables to test inputs of discriminators, then run existing 34-pair cable from SF to FC and look signals at CLAS trigger module and in ADCs, | |||
then decide on desired length of 34-pair cable and run it when FC is in normal position; propagation through detectors still must be estimated | |||
software: GUI is done, under testing, plan test for Friday; scripts and EPICS TO BE ADJUSTED; need some trigger logic test; need to make sure everybody have the same map, ADC and TDC and trigger; Pawel will prepare lookuptable procedures; Hovanes may need to modify EPICS GUIs, Sergey B. need to fix EPICS stuff | |||
* adcs/tdcs/scalers | * adcs/tdcs/scalers | ||
mini-VME64X borrowed from Chris and installed in the rack with splitters; mvme6100 CPU, TI and 4 v1190 TDC boards are installed | mini-VME64X borrowed from Chris and installed in the rack with splitters; mvme6100 CPU, TI and 4 v1190 TDC boards are installed; may need DAQ scalers, for example OR outputs from discriminators | ||
CC1 and EC2 swapped contents; CC1 has IC and Hodoscope ADCs (8 total); gate signals to be swapped | |||
Latest revision as of 10:17, 17 September 2008
present: Sergey Boyarinov, Valery Kubarovsky, Chris Cuevas, Ben Raydo, Sergey Pozdnyakov, Pawel Nadel-Turonski
- dvcs trigger
racks will be in final destination today
all discriminators have test inputs connected ( 6 groups 5-6 boards each), signals looks fine; width must be more then 25ns, otherwise built-in scalers can miss them (40ns will be fine)
one pulser (from FC)
measure cables to test inputs of discriminators, then run existing 34-pair cable from SF to FC and look signals at CLAS trigger module and in ADCs, then decide on desired length of 34-pair cable and run it when FC is in normal position; propagation through detectors still must be estimated
software: GUI is done, under testing, plan test for Friday; scripts and EPICS TO BE ADJUSTED; need some trigger logic test; need to make sure everybody have the same map, ADC and TDC and trigger; Pawel will prepare lookuptable procedures; Hovanes may need to modify EPICS GUIs, Sergey B. need to fix EPICS stuff
- adcs/tdcs/scalers
mini-VME64X borrowed from Chris and installed in the rack with splitters; mvme6100 CPU, TI and 4 v1190 TDC boards are installed; may need DAQ scalers, for example OR outputs from discriminators
CC1 and EC2 swapped contents; CC1 has IC and Hodoscope ADCs (8 total); gate signals to be swapped