VMM3 - Revision history

Boiarino at 15:29, 1 October 2024

2024-10-01T15:29:33Z

← Older revision		Revision as of 11:29, 1 October 2024
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	following menu command, read existing config vmm.txt, change settings, and write new config to the file		following menu command, read existing config vmm.txt, change settings, and write new config to the file
	move symbolic link vmm.txt to the new file		move symbolic link vmm.txt to the new file

			'''Parameters which can be changed using commands'''

			latency: before Prestart: tcpClient clondaq9 'vmmSetWindowParameters(78,4)' (latency and window size in 24ns ticks)

	'''Running modes with TI:'''		'''Running modes with TI:'''

Boiarino at 15:18, 1 October 2024

2024-10-01T15:18:51Z

← Older revision		Revision as of 11:18, 1 October 2024
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			'''Change configuration file'''

			goto $CLON_PARMS/vmm/
			run command 'vmm_create_cfg_file_L0'
			following menu command, read existing config vmm.txt, change settings, and write new config to the file
			move symbolic link vmm.txt to the new file

	'''Running modes with TI:'''		'''Running modes with TI:'''

Boiarino at 15:14, 1 October 2024

2024-10-01T15:14:52Z

← Older revision		Revision as of 11:14, 1 October 2024
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	[https://clonwiki0.jlab.org/wiki/clondocs/Docs/VMM_prototype_for_SoLID-Real_Time_2022.pdf VMM Based Readout Prototype for GEM detectors by Ed Jastrzembski (August 2022)]		[https://clonwiki0.jlab.org/wiki/clondocs/Docs/VMM_prototype_for_SoLID-Real_Time_2022.pdf VMM Based Readout Prototype for GEM detectors by Ed Jastrzembski (August 2022)]

	[https://clonwiki0.jlab.org/wiki/clondocs/Docs/vmm3a_GGGGG.pdf ATLAS NSW Electronics Speciﬁcations, Component: VMM3a (April 23, 2018)]		=useful==> [https://clonwiki0.jlab.org/wiki/clondocs/Docs/vmm3a_GGGGG.pdf ATLAS NSW Electronics Speciﬁcations, Component: VMM3a (April 23, 2018)]

	[https://clonwiki0.jlab.org/wiki/clondocs/Docs/VMM_2019_06_04_Iakovidis_VMM_GGGGG.pdf VMM ASIC by George Iakovidis, Brookhaven (04/06/2019)]		[https://clonwiki0.jlab.org/wiki/clondocs/Docs/VMM_2019_06_04_Iakovidis_VMM_GGGGG.pdf VMM ASIC by George Iakovidis, Brookhaven (04/06/2019)]

Boiarino at 20:14, 19 September 2024

2024-09-19T20:14:53Z

← Older revision		Revision as of 16:14, 19 September 2024
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	'''Running modes with TI:'''		'''Running modes with TI:'''

			To use prototype clock: connect prototype clock output (pins 9/10 of the connector on FPGA side) to prototype CLOCK IN.
			To use TI clock: connect TI clock output (pins 39/40) to prototype CLOCK IN, set TI clock output to 41.7MHz.

	'''Using pulser on prototype:'''		'''Using pulser on prototype:'''
	~~Connect prototype pulser output (pins 9/10 of the connector on FPGA side) to prototype CLOCK IN.~~
	Connect prototype AUX OUT to TI trigger input (pins 31/32 if TS#5 is used).		Connect prototype AUX OUT to TI trigger input (pins 31/32 if TS#5 is used).
	Connect TI Prompt Trigger Out (pins 15/16) to prototype TRIG IN.		Connect TI Prompt Trigger Out (pins 15/16) to prototype TRIG IN.

Boiarino: /* VMM3 prototype */

2024-09-19T15:40:29Z

VMM3 prototype

← Older revision		Revision as of 11:40, 19 September 2024
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	Program the internal pulser rate.		Program the internal pulser rate.
	Program the delay between hit and trigger that matches the Latency in the VMM Configuration file.		Program the delay between hit and trigger that matches the Latency in the VMM Configuration file.
	'''Description of mode:''' The internal pulser is enabled by selecting CKTP as 'internal pulser'.		'''Description of mode:'''
			The internal pulser is enabled by selecting CKTP as 'internal pulser'.
	The Test Pulse promptly generates hits in the channels selected in the VMM Configuration file and is also driven off board on AUX OUT.		The Test Pulse promptly generates hits in the channels selected in the VMM Configuration file and is also driven off board on AUX OUT.
	The L1 Accept from the TI is the TRIG IN signal which is delayed in the prototype by the programmed amount ( = Latency).		The L1 Accept from the TI is the TRIG IN signal which is delayed in the prototype by the programmed amount ( = Latency).
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	Program the delay between hit and trigger that matches the Latency in the VMM Configuration file.		Program the delay between hit and trigger that matches the Latency in the VMM Configuration file.
	Program and start pulser on TI.		Program and start pulser on TI.
	'''Description of mode:''' By selecting CKTP as 'external trigger' the TRIG IN signal will generate the Test Pulse. The internal pulser on the prototype is not enabled.		'''Description of mode:'''
	The Test Pulse promptly generates hits in the channels selected in the VMM Configuration file. TRIG IN is delayed in the prototype by the programmed amount ( = Latency) and serves as the VMM trigger.		By selecting CKTP as 'external trigger' the TRIG IN signal will generate the Test Pulse.
			The internal pulser on the prototype is not enabled.
			The Test Pulse promptly generates hits in the channels selected in the VMM Configuration file.
			TRIG IN is delayed in the prototype by the programmed amount ( = Latency) and serves as the VMM trigger.

	'''Detector Mode:''' Connect TI ~~L1 Accept~~ to prototype TRIG IN. Select Trigger Source as 'external' (0). Select Test Pulse Source (CKTP) as 'none' (0).		'''Detector Mode:'''
			Connect TI Prompt Trigger Out (pins 15/16) to prototype TRIG IN.
			Select Trigger Source as 'external' (0).
			Select Test Pulse Source (CKTP) as 'none' (0).
	Program the Latency in the VMM Configuration file to match the expected HIT - TRIGGER time difference.		Program the Latency in the VMM Configuration file to match the expected HIT - TRIGGER time difference.
	'''Description of mode:''' By selecting CKTP as 'none' the internal pulser is not enabled. The TRIG IN signal will be promptly sent as the VMM trigger.		'''Description of mode:'''
			By selecting CKTP as 'none' the internal pulser is not enabled.
			The TRIG IN signal will be promptly sent as the VMM trigger.

Boiarino at 15:37, 19 September 2024

2024-09-19T15:37:09Z

← Older revision		Revision as of 11:37, 19 September 2024
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	The delayed trigger is the VMM Trigger. (The delay may have to be set slightly less than the Latency due to the TI IN-OUT delay.)		The delayed trigger is the VMM Trigger. (The delay may have to be set slightly less than the Latency due to the TI IN-OUT delay.)

	'''Using pulser on TI:''' Connect TI ~~L1 Accept~~ to prototype TRIG IN. Select Trigger Source as 'external delayed' (1).		'''Using pulser on TI:'''
	Select Test Pulse Source (CKTP) as 'external trigger' (1). Program the delay between hit and trigger that matches the Latency in the VMM Configuration file.		Connect TI Prompt Trigger Out (pins 15/16) to prototype TRIG IN.
			Select Trigger Source as 'external delayed' (1).
			Select Test Pulse Source (CKTP) as 'external trigger' (1).
			Program the delay between hit and trigger that matches the Latency in the VMM Configuration file.
	Program and start pulser on TI.		Program and start pulser on TI.
	'''Description of mode:''' By selecting CKTP as 'external trigger' the TRIG IN signal will generate the Test Pulse. The internal pulser on the prototype is not enabled.		'''Description of mode:''' By selecting CKTP as 'external trigger' the TRIG IN signal will generate the Test Pulse. The internal pulser on the prototype is not enabled.
	The Test Pulse promptly generates hits in the channels selected in the VMM Configuration file. TRIG IN is delayed in the prototype by the programmed amount ( = Latency) and serves as the VMM trigger.		The Test Pulse promptly generates hits in the channels selected in the VMM Configuration file. TRIG IN is delayed in the prototype by the programmed amount ( = Latency) and serves as the VMM trigger.

Boiarino at 15:35, 19 September 2024

2024-09-19T15:35:09Z

← Older revision		Revision as of 11:35, 19 September 2024
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	Connect prototype pulser output (pins 9/10 of the connector on FPGA side) to prototype CLOCK IN.		Connect prototype pulser output (pins 9/10 of the connector on FPGA side) to prototype CLOCK IN.
	Connect prototype AUX OUT to TI trigger input (pins 31/32 if TS#5 is used).		Connect prototype AUX OUT to TI trigger input (pins 31/32 if TS#5 is used).
	Connect TI ~~L1 Accept~~ (pins 15/16) to prototype TRIG IN.		Connect TI Prompt Trigger Out (pins 15/16) to prototype TRIG IN.
	Select Trigger Source as 'external delayed' (1).		Select Trigger Source as 'external delayed' (1).
	Select Test Pulse Source (CKTP) as 'internal pulser' (2).		Select Test Pulse Source (CKTP) as 'internal pulser' (2).

Boiarino at 15:32, 19 September 2024

2024-09-19T15:32:44Z

← Older revision		Revision as of 11:32, 19 September 2024
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	'''Using pulser on prototype:'''		'''Using pulser on prototype:'''
	Connect prototype pulser output (pins 9/10 of the connector on FPGA side) to prototype CLOCK IN.		Connect prototype pulser output (pins 9/10 of the connector on FPGA side) to prototype CLOCK IN.
	Connect prototype AUX OUT to TI trigger input.		Connect prototype AUX OUT to TI trigger input (pins 31/32 if TS#5 is used).
	Connect TI L1 Accept to prototype TRIG IN.		Connect TI L1 Accept (pins 15/16) to prototype TRIG IN.
	Select Trigger Source as 'external delayed' (1).		Select Trigger Source as 'external delayed' (1).
	Select Test Pulse Source (CKTP) as 'internal pulser' (2).		Select Test Pulse Source (CKTP) as 'internal pulser' (2).

Boiarino at 15:30, 19 September 2024

2024-09-19T15:30:57Z

← Older revision		Revision as of 11:30, 19 September 2024
Line 30:		Line 30:

	'''Using pulser on prototype:'''		'''Using pulser on prototype:'''
	Connect prototype pulser output (pins 9/10 on FPGA side) to		Connect prototype pulser output (pins 9/10 of the connector on FPGA side) to prototype CLOCK IN.
	Connect prototype AUX OUT to TI trigger input.		Connect prototype AUX OUT to TI trigger input.
	Connect TI L1 Accept to prototype TRIG IN.		Connect TI L1 Accept to prototype TRIG IN.

Boiarino at 15:29, 19 September 2024

2024-09-19T15:29:59Z

← Older revision		Revision as of 11:29, 19 September 2024
Line 30:		Line 30:

	'''Using pulser on prototype:'''		'''Using pulser on prototype:'''
			Connect prototype pulser output (pins 9/10 on FPGA side) to
	Connect prototype AUX OUT to TI trigger input.		Connect prototype AUX OUT to TI trigger input.
	Connect TI L1 Accept to prototype TRIG IN.		Connect TI L1 Accept to prototype TRIG IN.