VHDL programming - Revision history

98.166.92.51: /* Basic rules for V1495-based CLAS triggers */

2011-08-07T19:39:09Z

Basic rules for V1495-based CLAS triggers

← Older revision		Revision as of 15:39, 7 August 2011
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	end process;		end process;

	8. Actual mapping for components described above. Multiple copies of the same component can be created (6 in our example). In ''port map'' section, signals on the left are component IO signal names as they appeares in the component definition, and signals on the right are local signals. Index ''I'' is used in mapping to connect different copies of the component the desired way.		8. Actual mapping for components described above. Multiple copies of the same component can be created (6 in our example). In ''port map'' section, signals on the left are component IO signal names as they appeares in the component definition, and signals on the right are local signals or port signals. Index ''I'' is used in mapping to connect different copies of the component the desired way.
	SectorLogicGen: for I in 0 to 5 generate		SectorLogicGen: for I in 0 to 5 generate
	SectorPeripheral_SectorN: SectorPeripheral		SectorPeripheral_SectorN: SectorPeripheral

2011-08-07T18:43:02Z

Basic rules for V1495-based CLAS triggers

2011-08-07T18:42:03Z

Basic rules for V1495-based CLAS triggers

← Older revision		Revision as of 14:42, 7 August 2011
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	end process;		end process;

	8. Actual mapping for components described above. Multiple copies of the same component can be created (6 in our example). In ''port map'' section, signals on the left are component IO signal names as they appeares in the component definition, and signals on the right are local signals.		8. Actual mapping for components described above. Multiple copies of the same component can be created (6 in our example). In ''port map'' section, signals on the left are component IO signal names as they appeares in the component definition, and signals on the right are local signals. Index ''I'' is used in mapping to connect different copies of the component the desired way.
	SectorLogicGen: for I in 0 to 5 generate		SectorLogicGen: for I in 0 to 5 generate
	SectorPeripheral_SectorN: SectorPeripheral		SectorPeripheral_SectorN: SectorPeripheral
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	LCLK => LCLK,		LCLK => LCLK,
	ADDR => USER_ADDR,		ADDR => USER_ADDR,
	-- and so on		DIN => USER_DIN,
			DOUT => USER_DOUT_MUXIN(I),
			-- and so on
	);		);
	end generate;		end generate;

2011-08-07T18:39:03Z

Basic rules for V1495-based CLAS triggers

← Older revision		Revision as of 14:39, 7 August 2011
Line 57:		Line 57:
	end process;		end process;

	8.		8. Actual mapping for components described above. Multiple copies of the same component can be created (6 in our example). In ''port map'' section, signals on the left are component IO signal names as they appeares in the component definition, and signals on the right are local signals.
	SectorLogicGen: for I in 0 to 5 generate		SectorLogicGen: for I in 0 to 5 generate
	SectorPeripheral_SectorN: SectorPeripheral		SectorPeripheral_SectorN: SectorPeripheral

2011-08-07T18:34:36Z

Basic rules for V1495-based CLAS triggers

← Older revision		Revision as of 14:34, 7 August 2011
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	end if;		end if;
	end process;		end process;

			8.
			SectorLogicGen: for I in 0 to 5 generate
			SectorPeripheral_SectorN: SectorPeripheral
			generic map(
			BASE_ADDR => x"10" + conv_std_logic_vector(I, 8)
			)
			port map(
			RESET => SYS_RESET,
			ENABLE_SCALERS => ENABLE_SCALERS,
			LCLK => LCLK,
			ADDR => USER_ADDR,
			-- and so on
			);
			end generate;

2011-08-07T14:10:45Z

Basic rules for V1495-based CLAS triggers

← Older revision		Revision as of 10:10, 7 August 2011
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	nLEDR <= PLL_LOCK;		nLEDR <= PLL_LOCK;
	SYS_RESET <= not nLBRES;		SYS_RESET <= not nLBRES;

			7. Process(es) declarations; processes are executed if one of the signals in parameter's list was changed (in this example it is LCLK)
			process(LCLK)
			begin
			if rising_edge(LCLK) then
			HEART_BEAT_CNT <= HEART_BEAT_CNT + 1;
			end if;
			end process;

2011-08-07T14:06:50Z

← Older revision		Revision as of 10:06, 7 August 2011
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	signal USER_DOUT_MUXIN : UserBusArray;		signal USER_DOUT_MUXIN : UserBusArray;

	6.		6. ''Begin'' statement and ??initial signals settings??

			begin
			nLEDG <= not HEART_BEAT_CNT(25);
			nLEDR <= PLL_LOCK;
			SYS_RESET <= not nLBRES;

2011-08-07T14:04:34Z

Basic rules for V1495-based CLAS triggers

← Older revision		Revision as of 10:04, 7 August 2011
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	end component;		end component;

	5. Internal signals description (internal for this entity):		5. Internal signals, types, constnts description (internal for this entity):
	signal PLLCLK : std_logic;		signal PLLCLK : std_logic;
	signal HEART_BEAT_CNT : std_logic_vector(25 downto 0) := "00000000000000000000000000";		signal HEART_BEAT_CNT : std_logic_vector(25 downto 0) := "00000000000000000000000000";
	signal USER_DIN : std_logic_vector(31 downto 0);		signal USER_DIN : std_logic_vector(31 downto 0);
			constant NUM_USER_BUS : integer := 21;
			type UserBusArray is array(0 to NUM_USER_BUS-1) of std_logic_vector(31 downto 0);
			signal USER_DOUT_MUXIN : UserBusArray;

	6.		6.

2011-08-07T14:03:22Z

← Older revision		Revision as of 10:03, 7 August 2011
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	);		);
	end component;		end component;

			5. Internal signals description (internal for this entity):
			signal PLLCLK : std_logic;
			signal HEART_BEAT_CNT : std_logic_vector(25 downto 0) := "00000000000000000000000000";
			signal USER_DIN : std_logic_vector(31 downto 0);

			6.

2011-08-07T13:58:23Z

Basic rules for V1595-based CLAS triggers

← Older revision		Revision as of 09:58, 7 August 2011
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	== Basic rules for ~~V1595~~-based CLAS triggers ==		== Basic rules for V1495-based CLAS triggers ==

	In general VHDL files contains following sections:		In general VHDL files contains following sections:
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	end HallBTrigger;		end HallBTrigger;

	3. Actual body~~, where ''component'' describes another entity (just describes, actual include will be done below)~~		3. Actual body beginning:

	architecture Synthesis of HallBTrigger is		architecture Synthesis of HallBTrigger is

			4. Description of another entity (just describes, actual include will be done below)
	component SectorPeripheral is		component SectorPeripheral is
	generic(		generic(