October 3, 2007 online meeting minutes - Revision history

Boiarino at 02:42, 10 October 2007

2007-10-10T02:42:16Z

← Older revision		Revision as of 22:42, 9 October 2007
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	* sy1527 in epics: add reboot button into standard IOC reboot menu; reconnect is not implemented after hardware reboot, must be addressed		* sy1527 in epics: add reboot button into standard IOC reboot menu; reconnect is not implemented after hardware reboot, must be addressed

	* sy527 in epics: Sergey B. is working on it, will be done similar to sy1527's support but ~~for~~ vxWorks; it will run in VME crate because of VME v288 CAENET controller is used to talk to sy527 mainframes; first application will be LAC HV system; if successful, can be used for DC in parallel with DCHV program		* sy527 in epics: Sergey B. is working on it, will be done similar to sy1527's support but in vxWorks; it will run in VME crate because of VME v288 CAENET controller is used to talk to sy527 mainframes; first application will be LAC HV system; if successful, can be used for DC in parallel with DCHV program; those efforts is part of our monitoring system development: as we discussed before all information will be presented as EPICS CA to be available to higher level monitoring components

	* v1190/v1290 extensive testing with new firmware: CBLT and slot# problems will be investigated; install mv6100 in the hall, switch to 2eSST and run tests		* v1190/v1290 extensive testing with new firmware: CBLT and slot# problems will be investigated; install mv6100 in the hall, switch to 2eSST and run tests

Boiarino at 02:39, 10 October 2007

2007-10-10T02:39:05Z

← Older revision		Revision as of 22:39, 9 October 2007
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	'''Projects'''		'''Projects'''

	* PCAL (works, +5V fixed, signal ~~distr~~ board replaced, 1 sec delay introduced in 'go' to fix hunging; Stepan asked about		* PCAL test setup finally works: +5V fixed, signal distribution board replaced, 1 sec delay introduced in 'go' transition to fix hunging on the first event (must understand that !). Stepan asked about 10 times better ADC resolution: one of the options can be 2+ Gsample PCI card, but TI board in PCI format is needed. Need to ask Ed how that project is going.
	~~10times~~ better ADC resolution ~~- >2Gsample~~ card ~~???)~~

			* Active collimator probably needed in DAQ, will be discussed when decision will be made.

	* ~~TI in PCI - may need~~ it ~~again~~, ~~remind Ed~~		* Wolfram test setup works, ROOT too slow when attached to the ET system and holds data flow, it will be addressed during upcoming run preparations (select function, control word bit by EB ???).

	* ~~Active collimator needed in DAQ - probably~~		* For Lecroy mainframes were sent to be repaired.

	* ~~Wolfram (works~~, ~~ROOT too slow and will be addressed during upcoming run preparations (select function, control worls bit by EB ???))~~		* sy527 AC connectors arrived, we'll arrange replacement

			* Motorola seems agree to replace unrepairable PrPMC880 with equivalent board (newer version of PMC280), hopefully we can use it

	* Lecroy repairs, sy527 AC connectors replacement (will Chris)		* Frost preparations: all power turned on including DC FASTBUS crates, ethernet/serial cables ran for target platform; Carl still working on ET modifications, tests to be started shortly, new version expected in about a week, we'll wait for the final version, do modifications and then run full CLAS DAQ test; new EPICS channels from target maybe needed in data stream, and some of existing channels proably renaimed, need check

	* PrPMC880 replacement

	* Frost preparations: all power turned on including DC FASTBUS crates, ethernet/serial cables ran for target platform;
	Carl still working on ET modifications, tests to be started ~~dayli~~, new version expected in about a week, we'll wait, do
	modifications and then run full CLAS DAQ test; new EPICS channels from target

	TODO:		TODO:

	* sy1527: reboot button, reconnect after hardware reboot		* sy1527 in epics: add reboot button into standard IOC reboot menu; reconnect is not implemented after hardware reboot, must be addressed

	* sy527 support (similar to sy1527 but in VME crate because of VME CAENAT board v288)

	* ~~v1190/v1290 extensive testing (CBLT~~, ~~slot#~~, ~~install mv6100~~ in ~~the hall and switch to 2eSST)~~		* sy527 in epics: Sergey B. is working on it, will be done similar to sy1527's support but for vxWorks; it will run in VME crate because of VME v288 CAENET controller is used to talk to sy527 mainframes; first application will be LAC HV system; if successful, can be used for DC in parallel with DCHV program

	* ~~DVCS Trigger Development~~		* v1190/v1290 extensive testing with new firmware: CBLT and slot# problems will be investigated; install mv6100 in the hall, switch to 2eSST and run tests

	* Hall B electronics ~~inventarization~~		* Hall B electronics inventory - Sergey P. is working on it

	* Upcoming run preparations on requests (fix flip-related problem in online delay reporting correction procedure, ..)		* Upcoming run preparations on requests (fix flip-related problem in online delay reporting correction procedure, ..)

	* beam test with preshower during upcoming run - will ~~talk next week Stepan~~		* beam test with preshower during upcoming run - Stepan will present it on one of the future meetings


	* ~~probably~~ Hall D test in Hall B - next summer		* Hall D test may be conducted in Hall B some time next summer; since electronic pool does not exist people should think about equipment in advance

Boiarino at 02:05, 10 October 2007

2007-10-10T02:05:58Z

← Older revision		Revision as of 22:05, 9 October 2007
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	'''DVCS Trigger System'''		'''DVCS Trigger System'''

	Ben presented preliminary [http://clonweb/wiki/clondocs/DVCS_Trigger/PreliminaryDesign.ppt design] of the system. It based on v1495 boards equiped with A395A and A395D cards. System uses 200MHz clock wich 4-clock data processing cycles. There is no external start, system works as pipeline. In according to Stepan time difference between hits in the same cluster is smaller then few ns, so with processing clock 50MHz we will set discriminator's output signals to about 30ns to enforce coinsidence.		Ben presented preliminary [http://clonweb/wiki/clondocs/DVCS_Trigger/PreliminaryDesign.ppt design] of the system. It based on v1495 boards equiped with A395A and A395D cards. System uses 200MHz clock wich 4-clock data processing cycles. There is no external start, system works as pipeline. In according to Stepan time difference between hits in the same cluster is smaller then few ns, so with processing clock 50MHz we will set discriminator's output signals to about 30ns to enforce coinsidence. Preliminary Ben estimated that 8-9 cycles at 50MHz will be needed for the system to make the decision.

	Ben will continue with system simulation and i/o performance testing. We will prepare DVCS data file which can be used in simulation process. In about one month we'll make a final decision on hardware and order it. Preliminary, if current design will be used, we'll need following boards (with spares): v1495 (6 units), A395A (11 units), A395D (2 units). We may be able to borrow v1495 from other JLAB groups to speedup developing.		Ben will continue with system simulation and i/o performance testing. We will prepare DVCS data file which can be used in simulation process. In about one month we'll make a final decision on hardware and order it. Preliminary, if current design will be used, we'll need following boards (with spares): v1495 (6 units), A395A (11 units), A395D (2 units). We may be able to borrow v1495 from other JLAB groups to speedup developing.

Boiarino at 02:01, 10 October 2007

2007-10-10T02:01:43Z

← Older revision		Revision as of 22:01, 9 October 2007
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	Ben presented preliminary [http://clonweb/wiki/clondocs/DVCS_Trigger/PreliminaryDesign.ppt design] of the system. It based on v1495 boards equiped with A395A and A395D cards. System uses 200MHz clock wich 4-clock data processing cycles. There is no external start, system works as pipeline. In according to Stepan time difference between hits in the same cluster is smaller then few ns, so with processing clock 50MHz we will set discriminator's output signals to about 30ns to enforce coinsidence.		Ben presented preliminary [http://clonweb/wiki/clondocs/DVCS_Trigger/PreliminaryDesign.ppt design] of the system. It based on v1495 boards equiped with A395A and A395D cards. System uses 200MHz clock wich 4-clock data processing cycles. There is no external start, system works as pipeline. In according to Stepan time difference between hits in the same cluster is smaller then few ns, so with processing clock 50MHz we will set discriminator's output signals to about 30ns to enforce coinsidence.

			Ben will continue with system simulation and i/o performance testing. We will prepare DVCS data file which can be used in simulation process. In about one month we'll make a final decision on hardware and order it. Preliminary, if current design will be used, we'll need following boards (with spares): v1495 (6 units), A395A (11 units), A395D (2 units). We may be able to borrow v1495 from other JLAB groups to speedup developing.

			'''Projects'''

	Projects



	* PCAL (works, +5V fixed, signal distr board replaced, 1 sec delay introduced in 'go' to fix hunging; Stepan asked about		* PCAL (works, +5V fixed, signal distr board replaced, 1 sec delay introduced in 'go' to fix hunging; Stepan asked about

Boiarino at 01:52, 10 October 2007

2007-10-10T01:52:05Z

← Older revision		Revision as of 21:52, 9 October 2007
Line 3:		Line 3:
	'''DVCS Trigger System'''		'''DVCS Trigger System'''

	Ben presented preliminary [http://clonweb/wiki/clondocs/DVCS_Trigger/PreliminaryDesign.ppt design] of the system. It based on v1495 boards equiped with A395A and A395D cards. System uses 200MHz clock wich 4-clock data processing cycles. There is no external start, system works as pipeline. In according to Stepan time difference between hits in the same cluster is smaller then few ns, so with processing clock 50MHz we will set discriminator's output signals to about 30ns to ~~enforse~~ coinsidence.		Ben presented preliminary [http://clonweb/wiki/clondocs/DVCS_Trigger/PreliminaryDesign.ppt design] of the system. It based on v1495 boards equiped with A395A and A395D cards. System uses 200MHz clock wich 4-clock data processing cycles. There is no external start, system works as pipeline. In according to Stepan time difference between hits in the same cluster is smaller then few ns, so with processing clock 50MHz we will set discriminator's output signals to about 30ns to enforce coinsidence.

Boiarino at 01:50, 10 October 2007

2007-10-10T01:50:59Z

← Older revision		Revision as of 21:50, 9 October 2007
Line 3:		Line 3:
	'''DVCS Trigger System'''		'''DVCS Trigger System'''

	Ben presented preliminary [http://clonweb/wiki/clondocs/DVCS_Trigger/PreliminaryDesign.ppt design] of the system.		Ben presented preliminary [http://clonweb/wiki/clondocs/DVCS_Trigger/PreliminaryDesign.ppt design] of the system. It based on v1495 boards equiped with A395A and A395D cards. System uses 200MHz clock wich 4-clock data processing cycles. There is no external start, system works as pipeline. In according to Stepan time difference between hits in the same cluster is smaller then few ns, so with processing clock 50MHz we will set discriminator's output signals to about 30ns to enforse coinsidence.

Boiarino at 01:38, 10 October 2007

2007-10-10T01:38:59Z

← Older revision		Revision as of 21:38, 9 October 2007
Line 3:		Line 3:
	'''DVCS Trigger System'''		'''DVCS Trigger System'''

	Ben presented preliminary [[http://clonweb/wiki/clondocs/DVCS_Trigger/PreliminaryDesign.ppt design] of the system.		Ben presented preliminary [http://clonweb/wiki/clondocs/DVCS_Trigger/PreliminaryDesign.ppt design] of the system.

Boiarino at 01:37, 10 October 2007

2007-10-10T01:37:26Z

← Older revision		Revision as of 21:37, 9 October 2007
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	'''DVCS Trigger System'''		'''DVCS Trigger System'''

	Ben presented preliminary [design] of the system.		Ben presented preliminary [[http://clonweb/wiki/clondocs/DVCS_Trigger/PreliminaryDesign.ppt design] of the system.

Boiarino at 01:34, 10 October 2007

2007-10-10T01:34:19Z

← Older revision		Revision as of 21:34, 9 October 2007
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	present: Sergey Boyarinov, Sergey Pozdnyakov, Nerses Gevorgyan, Tanest Chinwanawich, Elliott Wolin, Benjamin Raydo, Stepan Stepanyan		present: Sergey Boyarinov, Sergey Pozdnyakov, Nerses Gevorgyan, Tanest Chinwanawich, Elliott Wolin, Benjamin Raydo, Stepan Stepanyan

			'''DVCS Trigger System'''

			Ben presented preliminary [design] of the system.
	~~DVCS Trigger System~~

Boiarino at 17:23, 9 October 2007

2007-10-09T17:23:37Z

← Older revision		Revision as of 13:23, 9 October 2007
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			present: Sergey Boyarinov, Sergey Pozdnyakov, Nerses Gevorgyan, Tanest Chinwanawich, Elliott Wolin, Benjamin Raydo, Stepan Stepanyan



	DVCS Trigger System		DVCS Trigger System