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	<title>October 25, 2017 online meeting minutes - Revision history</title>
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	<updated>2026-04-12T00:48:57Z</updated>
	<subtitle>Revision history for this page on the wiki</subtitle>
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		<id>https://clonwiki0.jlab.org/wiki/index.php?title=October_25,_2017_online_meeting_minutes&amp;diff=7153&amp;oldid=prev</id>
		<title>Boiarino: Created page with &quot;present: Sergey Boyarinov, Cole Smith, Chris Cuevas, Ben Raydo, Valery by bluejeans: Raffaella Devita, Andrea Celentano, Nick Markov (thanks to Nick Markov and Valery to set b...&quot;</title>
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		<updated>2017-10-25T15:11:07Z</updated>

		<summary type="html">&lt;p&gt;Created page with &amp;quot;present: Sergey Boyarinov, Cole Smith, Chris Cuevas, Ben Raydo, Valery by bluejeans: Raffaella Devita, Andrea Celentano, Nick Markov (thanks to Nick Markov and Valery to set b...&amp;quot;&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;present: Sergey Boyarinov, Cole Smith, Chris Cuevas, Ben Raydo, Valery&lt;br /&gt;
by bluejeans: Raffaella Devita, Andrea Celentano, Nick Markov&lt;br /&gt;
(thanks to Nick Markov and Valery to set bluejeans)&lt;br /&gt;
&lt;br /&gt;
1. CLAS12 trigger:&lt;br /&gt;
&lt;br /&gt;
* hardware: 12 recently installed VTPs being configured, DC done, FTOF almost done; 7 more VTPs did not pass acceptance test, problems identified and boards will be send for repair; 2-3 has good chances of repair in few days, others in couple of weeks;&lt;br /&gt;
SSSP fanout for HTCC installed, being cabled&lt;br /&gt;
&lt;br /&gt;
* cabling: in progress, fibers being reorganized and labeled; SVT fiber today, FC by Friday, DC next week; have to finish before RICH installation started&lt;br /&gt;
&lt;br /&gt;
* software:&lt;br /&gt;
&lt;br /&gt;
Rafo finished GEMC digitization for all needed detectors (ECAL/PCAL/HTCC/FT/FTOF), 2 files produced&lt;br /&gt;
&lt;br /&gt;
C++ implementation for all stage 1 trigger components are finished (ECAL/PCAL/HTCC some time ago, FT by Andrea and FTOF by Sergey/Ben recently)&lt;br /&gt;
&lt;br /&gt;
* testing on GEMC files is in progress: Sergey will make sure trigger banks are written to evil file, so we are ready for validation 1 (between hardware and C++ implementation); ... validation 2 ...&lt;br /&gt;
&lt;br /&gt;
* C++ simulation for stage 2 and 3 will start next week: Rafo will be leading developer, Ben and Sergey will provide framework&lt;br /&gt;
&lt;br /&gt;
* Andrea is ready to process FT-related data&lt;br /&gt;
&lt;br /&gt;
* trigger commissioning strategy was discussed; Ben recommended random trigger, 2.5M events gives 1 second of real data taking;&lt;br /&gt;
we discussed many issues, will proceed with the plan; Ben will send email about FT scalers/histos to be produced in trigger system;&lt;br /&gt;
tools to see fadc pulses to set day readout window are needed&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
2. DAQ preparations:&lt;br /&gt;
&lt;br /&gt;
* TDC calibration: we had organization meeting Monday on CAEN v1290 TDC calibration, Andrey Kim will be leading person, Sergey will prepare needed DAQ configuration, Ed and Bryan Moffit will provide expert support &lt;br /&gt;
&lt;br /&gt;
* CND: CAMAC C111C controller was installed, all hardware in place; need spare&lt;br /&gt;
&lt;br /&gt;
* 68-pin cables to be checked, one seems missing&lt;/div&gt;</summary>
		<author><name>Boiarino</name></author>
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