October 15, 2008 online meeting minutes - Revision history

98.166.91.3 at 02:22, 17 October 2008

2008-10-17T02:22:19Z

← Older revision		Revision as of 22:22, 16 October 2008
Line 1:		Line 1:
	present: Sergey Boyarinov, ~~Valeri~~, Ben, Chris Cuevas, Puneet, Sergey, Pawel		present: Sergey Boyarinov, Valery Kubarovsky, Ben Raydo, Chris Cuevas, Puneet Khetarpal, Sergey Pozdnyakov, Pawel Nadel-Turonsky

	* DVCS-CLAS trigger		* DVCS-CLAS trigger

Boiarino at 14:53, 15 October 2008

2008-10-15T14:53:04Z

← Older revision		Revision as of 10:53, 15 October 2008
Line 1:		Line 1:
	present: Sergey Boyarinov, Valeri, Ben, Chris Cuevas, ~~Penn~~, Sergey, Pawel		present: Sergey Boyarinov, Valeri, Ben, Chris Cuevas, Puneet, Sergey, Pawel

	* DVCS-CLAS trigger		* DVCS-CLAS trigger
Line 21:		Line 21:
	TO DO: DVCSTRIG test, gate cable, scope gate test, DAQ gate test, DVCS pedestal run; all-concidence-delay curve will be done with beam, need to write delays from script		TO DO: DVCSTRIG test, gate cable, scope gate test, DAQ gate test, DVCS pedestal run; all-concidence-delay curve will be done with beam, need to write delays from script

	'makelut' will be installed into $CODA area, README file exist		'makelut' will be installed into $CODA area, README file exist; it will write logic formula from C code into LUT file as a comment

	NEED TO COLLECT ALL DRAWINGS/DOCUMENTATIONS BEFORE RUN STARTS !!!		NEED TO COLLECT ALL DRAWINGS/DOCUMENTATIONS BEFORE RUN STARTS !!!

Boiarino at 14:28, 15 October 2008

2008-10-15T14:28:55Z

← Older revision		Revision as of 10:28, 15 October 2008
Line 1:		Line 1:
	present: Sergey Boyarinov, Valeri, Ben, Chris Cuevas, Penn, Sergey		present: Sergey Boyarinov, Valeri, Ben, Chris Cuevas, Penn, Sergey, Pawel

	* DVCS-CLAS trigger		* DVCS-CLAS trigger
Line 9:		Line 9:

	forward carreage is in position and DVCS-CLASTRIG cable was can to the nominal length, signal is in gate about 30ns from		forward carreage is in position and DVCS-CLASTRIG cable was can to the nominal length, signal is in gate about 30ns from
	the beginning of the gate pulse, gate cables is in production, hope to get another 20ns		the beginning of the gate pulse, gate cables is in production, hope to get another 20ns; we will make gate-signal coincidence curve with DVCS laser with DAQ

	EPICS readout for scalers in both CLASTRIG2 and DVCSTRIG is working, scaler histograms and corresponding MEDM GUIs to be checked; normally all scalers will be reported in Hz; all quadrons counts equally		EPICS readout for scalers in both CLASTRIG2 and DVCSTRIG is working, scaler histograms and corresponding MEDM GUIs to be checked; normally all scalers will be reported in Hz; all quadrons counts equally

	Ben developed pattern test for the CLASTRIG2, extra v1495 board was installed in clastrig2 and connected to the main v1495, test was started from Windows GUI and passed successfully; DVCSTRIG test to be conducted - VERY IMPORTANT ! also ~~wiil~~ look at polarity of the optput cables		Ben developed pattern test for the CLASTRIG2, extra v1495 board was installed in clastrig2 and connected to the main v1495, test was started from Windows GUI and passed successfully including loading by scripts; DVCSTRIG test to be conducted - VERY IMPORTANT ! also will look at polarity of the optput cables

	trigger downloading scripts were adjusted, downloading/uploading works fine, uploading LUT still not implemented		trigger downloading scripts were adjusted, downloading/uploading works fine, uploading LUT still not implemented

	L2 to be tested		L2 to be tested

			TO DO: DVCSTRIG test, gate cable, scope gate test, DAQ gate test, DVCS pedestal run; all-concidence-delay curve will be done with beam, need to write delays from script

			'makelut' will be installed into $CODA area, README file exist

			NEED TO COLLECT ALL DRAWINGS/DOCUMENTATIONS BEFORE RUN STARTS !!!

Boiarino at 14:03, 15 October 2008

2008-10-15T14:03:45Z

← Older revision		Revision as of 10:03, 15 October 2008
Line 13:		Line 13:
	EPICS readout for scalers in both CLASTRIG2 and DVCSTRIG is working, scaler histograms and corresponding MEDM GUIs to be checked; normally all scalers will be reported in Hz; all quadrons counts equally		EPICS readout for scalers in both CLASTRIG2 and DVCSTRIG is working, scaler histograms and corresponding MEDM GUIs to be checked; normally all scalers will be reported in Hz; all quadrons counts equally

	Ben developed pattern test for the CLASTRIG2, extra v1495 board was installed in clastrig2 and connected to the main v1495, test was started from Windows GUI and passed successfully; DVCSTRIG test to be conducted - VERY IMPORTANT ! also wiil look at polarity of the optput cables		Ben developed pattern test for the CLASTRIG2, extra v1495 board was installed in clastrig2 and connected to the main v1495, test was started from Windows GUI and passed successfully; DVCSTRIG test to be conducted - VERY IMPORTANT ! also wiil look at polarity of the optput cables

	trigger downloading scripts were adjusted, downloading/uploading works fine, uploading LUT still not implemented		trigger downloading scripts were adjusted, downloading/uploading works fine, uploading LUT still not implemented

	L2 to be tested		L2 to be tested

Boiarino at 14:03, 15 October 2008

2008-10-15T14:03:37Z

← Older revision		Revision as of 10:03, 15 October 2008
Line 13:		Line 13:
	EPICS readout for scalers in both CLASTRIG2 and DVCSTRIG is working, scaler histograms and corresponding MEDM GUIs to be checked; normally all scalers will be reported in Hz; all quadrons counts equally		EPICS readout for scalers in both CLASTRIG2 and DVCSTRIG is working, scaler histograms and corresponding MEDM GUIs to be checked; normally all scalers will be reported in Hz; all quadrons counts equally

	Ben developed pattern test for the CLASTRIG2, extra v1495 board was installed in clastrig2 and connected to the main v1495, test was started from Windows GUI and passed successfully; DVCSTRIG test to be conducted - VERY IMPORTANT !		Ben developed pattern test for the CLASTRIG2, extra v1495 board was installed in clastrig2 and connected to the main v1495, test was started from Windows GUI and passed successfully; DVCSTRIG test to be conducted - VERY IMPORTANT ! also wiil look at polarity of the optput cables

	trigger downloading scripts were adjusted, downloading/uploading works fine, uploading LUT still not implemented		trigger downloading scripts were adjusted, downloading/uploading works fine, uploading LUT still not implemented

	L2 to be tested		L2 to be tested

Boiarino at 14:02, 15 October 2008

2008-10-15T14:02:30Z

@@ Line 1: / Line 1: @@
-present: Sergey Boyarinov,
+present: Sergey Boyarinov, Valeri, Ben, Chris Cuevas, Penn, Sergey
 * DVCS-CLAS trigger
@@ Line 10: / Line 10: @@
 forward carreage is in position and DVCS-CLASTRIG cable was can to the nominal length, signal is in gate about 30ns from
 the beginning of the gate pulse, gate cables is in production, hope to get another 20ns

Boiarino at 13:52, 15 October 2008

2008-10-15T13:52:33Z

New page

present: Sergey Boyarinov,

* DVCS-CLAS trigger

third rack was installed to make cabeling easy; all racks connected to the clean power, one more power strip was ordered
to use second 20A circuit

cabling between splitters and discriminators has been started in according to the Ben's map

forward carreage is in position and DVCS-CLASTRIG cable was can to the nominal length, signal is in gate about 30ns from
the beginning of the gate pulse, gate cables is in production, hope to get another 20ns