Boiarino: Created page with "present: Sergey Boyarinov, Chris Cuevas, Ben Raydo, Bryan Moffit, David Abbott 1. CLAS12 crate trigger processor * board name will be VTP (VXS Trigger Processor) * reasons:..."

2016-01-13T14:47:52Z

Created page with "present: Sergey Boyarinov, Chris Cuevas, Ben Raydo, Bryan Moffit, David Abbott 1. CLAS12 crate trigger processor * board name will be VTP (VXS Trigger Processor) * reasons:..."

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present: Sergey Boyarinov, Chris Cuevas, Ben Raydo, Bryan Moffit, David Abbott

1. CLAS12 crate trigger processor

* board name will be VTP (VXS Trigger Processor)

* reasons: 4 lines from each payload, bigger FPGA (V7) for CLAS12 needs, built-in processor on mezzanine (ARM 2/4 core running CODA), increase IN (5Gbit per line, still 2.5 for FADC250) and OUT (4 fibers (20Gbit each) and 10GBit ethernet) bandwidth; bandwidth between V7 and ARM and ethernet speed from ARM out need to be increased to 10Gbit at least; Ben will finalize design

* possibility to use lines from payloads to send data, not only trigger info

* out fiber can be used to connect several VTPs (connect few first-stage crates)

* final diagram end of February, design end of May, bid 25 in June (about $100K, contruct in July/August (2 first article), first article should be here in October-November; may buy some components early

* will consider future extension to 40GBit ethernet (may need if VME not used for readout and 5G/4lines can be used

2. HPS run preparations

February 4, 2015 online meeting minutes - Revision history

Boiarino: Created page with "present: Sergey Boyarinov, Chris Cuevas, Ben Raydo, Bryan Moffit, David Abbott 1. CLAS12 crate trigger processor * board name will be VTP (VXS Trigger Processor) * reasons:..."