February 25, 2009 online meeting minutes - Revision history

Boiarino at 17:00, 25 February 2009

2009-02-25T17:00:51Z

← Older revision		Revision as of 13:00, 25 February 2009
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	* Sergey B. is working to implement recovery procedure to have in DB runs with failed end		* Sergey B. is working to implement recovery procedure to have in DB runs with failed end

			* SUN intel-based clon01 arrived, will be commission; XRT graph license connected to existing machine, need to be resolved

			* automount problem with silo staging area, will be reported to CC

Boiarino at 16:37, 25 February 2009

2009-02-25T16:37:02Z

← Older revision		Revision as of 12:37, 25 February 2009
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	* + OR for trigger output, same time as signal on trigger output connector (NIM)		* + OR for trigger output, same time as signal on trigger output connector (NIM)

	* + user code in FPGA (left-right compensation, etc) - will be a space in main FPGA chip		* + user code in FPGA (left-right compensation, etc) - will not implement anything but will be a space in main FPGA chip

	* + VME readout: write/read all registers, A32/D64 with DMA		* + VME readout: write/read all registers, A32/D64 with DMA

Boiarino at 16:36, 25 February 2009

2009-02-25T16:36:22Z

← Older revision		Revision as of 12:36, 25 February 2009
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	present: Sergey Boyarinov, Sergey Pozdnyakov, Nerses Gevorgyan, Ben Raydo, Chris Cuevas		present: Sergey Boyarinov, Sergey Pozdnyakov, Nerses Gevorgyan, Ben Raydo, Chris Cuevas

	1. JLAB ~~discriminators~~		1. JLAB discriminator


	+ range 0-1V, accuracy is +-3mV, step 0.25mV; there is temperature dependence - to be documented		+ range 0-1V, accuracy is +-3mV, step 0.25mV; there is temperature dependence - to be documented

Boiarino at 16:35, 25 February 2009

2009-02-25T16:35:59Z

← Older revision		Revision as of 12:35, 25 February 2009
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	* + VME firmware upgrade		* + VME firmware upgrade


			2. eg1dvcs run status

			* BASEB must be modified (symb likns, top make file etc), maybe redirect epics's make application to our BASEB - Nerses

			* ECHV1 boards sometimes trips, we believe that it is related to bad connectors; trying to push pins in

			* Sergey B. is working to implement recovery procedure to have in DB runs with failed end

Boiarino at 16:24, 25 February 2009

2009-02-25T16:24:48Z

← Older revision		Revision as of 12:24, 25 February 2009
Line 1:		Line 1:
	present: Sergey Boyarinov		present: Sergey Boyarinov, Sergey Pozdnyakov, Nerses Gevorgyan, Ben Raydo, Chris Cuevas

	1. JLAB discriminators		1. JLAB discriminators

	* remove preamplifiers (at least reduce gain): can be done by not-installing some components; different amplifiers can be installed

	* mask outputs		+ range 0-1V, accuracy is +-3mV, step 0.25mV; there is temperature dependence - to be documented

	* ~~add test input: directly~~ to ~~digital side~~		* + preamplifiers will stay but gain reduced to 2 from 4; gain can be changed by changing resistors (soldered)

	* ~~individual channel thresholds, min 10 mV - real~~		* + positive pulse will not harm

	* ~~add second~~ output ~~connector (or high dense connector ?~~)~~: yes~~		* + mask outputs: can disable all, enable all, disable trigger outputs only (cannot disable tdc output only), all individual channels

	* ~~different thresholds for output 1 and output 2 (optional; maybe sacrofise individual threshold, maybe groups of 4 etc)~~		* + add test input: directly to digital side

	* individual ~~programmable width step~~: ~~8ns -> 4ns~~, the ~~less the better; max=100ns; non-updating mode~~		* + individual channel thresholds, min 10 mV - real: will try to satisfy (histeresis is set t0 5mV, so 10mVthreshold is on the edge)

	* ~~channel-based output delays for trigger~~ output connector - ~~optional, 500ns max~~		* + add second output connector: yes, 2 34-pin

	* ~~32-channel: will try~~ (~~backplane~~ board ?)		* + different thresholds for output 1 and output 2 (optional on the board)

	* ~~fast enough:~~ min ~~150MHz~~		* + individual programmable width for trigger, step 4ns, min 4ns; for tdc output is common, 10ns min, at least 4ns step; max=100ns; non-updating mode

	* ~~internal delay~~ (~~20 ns is Ok~~)		* + channel-based output delays for trigger output connector - about 20ns constant part, plus 4ns step (remember jitter 4ns !), 512ns max

	* ~~thermodrift~~ - ~~to be studied~~		* + 16-channel board !!!

	* ~~remove monitor~~		* + fast enough: 100MHz (double pulse res 11ns)

	* ~~not-stop scaler readout - optional~~		* + internal delay (trigger is 20ns, tdc is less then 10ns)

	* ~~keep gate/veto (2 inputs)~~		* + thermodrift - to be studied on prototype

	* ~~OR for trigger output (NIM)~~		* + remove monitor

	* VME readout: write/read all registers, A32/D64 with DMA		* + not-stop scaler readout

			* + 2 set of 32-bit scalers, one of then has external gate

			* + OR for trigger output, same time as signal on trigger output connector (NIM)

			* + user code in FPGA (left-right compensation, etc) - will be a space in main FPGA chip

			* + VME readout: write/read all registers, A32/D64 with DMA

			* + VME firmware upgrade

Boiarino at 14:46, 25 February 2009

2009-02-25T14:46:12Z

← Older revision		Revision as of 10:46, 25 February 2009
Line 2:		Line 2:

	1. JLAB discriminators		1. JLAB discriminators

			* remove preamplifiers (at least reduce gain): can be done by not-installing some components; different amplifiers can be installed

			* mask outputs

			* add test input: directly to digital side

			* individual channel thresholds, min 10 mV - real

			* add second output connector (or high dense connector ?): yes

			* different thresholds for output 1 and output 2 (optional; maybe sacrofise individual threshold, maybe groups of 4 etc)

			* individual programmable width step: 8ns -> 4ns, the less the better; max=100ns; non-updating mode

			* channel-based output delays for trigger output connector - optional, 500ns max

			* 32-channel: will try (backplane board ?)

			* fast enough: min 150MHz

			* internal delay (20 ns is Ok)

			* thermodrift - to be studied

			* remove monitor

			* not-stop scaler readout - optional

			* keep gate/veto (2 inputs)

			* OR for trigger output (NIM)

			* VME readout: write/read all registers, A32/D64 with DMA

Boiarino at 14:44, 25 February 2009

2009-02-25T14:44:22Z

New page

present: Sergey Boyarinov

1. JLAB discriminators