| CAEN C894 |
| 16 Channel Leading Edge Discriminator |
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| Family: CAMAC |
| - Individually programmable thresholds |
| - Selectable Updating/ Non Updating mode |
| - ECL outputs with fan out of two |
| - Programmable output width |
| - OR, Majority and Current Sum outputs |
| - TEST and VETO inputs |
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Overview |
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The Mod. C894 is a 16 Channel Leading Edge Discriminator housed in a single width CAMAC module. The module accepts 16 negative inputs (positive on request) and produces 16 differential ECL outputs with a fan-out of two on two front panel header connectors. The pulse forming stage of the discriminator produces an output pulse whose width is adjustable in a range from 5 ns to 40 ns. Each channel can work both in Updating and Non-Updating mode according to on-board jumpers position. The discriminator thresholds are individually settable in a range from -1 mV to -255 mV (1 mV step), via CAMAC through an 8-bit DAC. VETO and TEST inputs are available on the back panel. A Current Sum output generates a current proportional to the input multiplicity, i. e. to the number of channels over threshold, at a rate of -1.0 mA per hit ±20%. A "MAJORITY" output on a back panel connector provides a NIM signal if the number of input channels over threshold exceeds the MAJORITY programmed value. Several C894 boards can be connected in a daisy chain via the Current Sum output: in this case, by switching the Majority logic to "External", it's possible to obtain a Majority signal when the number of over threshold channels in the daisy chained modules exceeds a global Majority level. An "OR" output on a front panel connector provides a global OR of the output channels. |
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Technical Specification Table |
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Packaging | 1U-wide CAMAC unit | |||
| Threshold range | -1 mV to -255 mV (1 mV step) | ||||
| Inputs Channels | 16 inputs negative polarity, 50 Ohm impedance, DC coupling | ||||
| Reflections | <4% for input pulses of 2 ns rise time | ||||
| Max Inpu Voltage | -5 V | ||||
| Max input frequency | 140 Mhz (Updating mode) 80 Mhz (Non Updating mode) |
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| Double Pulse Resolution | 7 ns (Updating mode) 12 ns (Non Updating mode) |
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| Test Input | Std. NIM logic signal, high impedance Max. frequency: 60 Mhz Min. FWHM: 5 ns. |
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| Test/Output delay | 17 ± 1.5 ns | ||||
| Veto Input | NIM logic signal; High impedance; 15 ns min. FWHM | ||||
| Outputs | 16 ECL outputs on 110 Ohm with a fan-out of two | ||||
| Output width | 5±1 ns to 40±5 ns FWHM | ||||
| Input/output delay | 18 ± 1 ns | ||||
| Majority output | NIM logic signal; 50 Ohm impedance | ||||
| Or output | NIM logic signal; 50 Ohm impedance | ||||
| Current Sum output | -1 mA ± 20% per hit; High impedance |