¥- existing pretrigger system (CAMAC-
and VME/VXI-based discriminators accepting data from scintillator-based
detectors and producing signals for Level1 logic) will be removed
completely if FADCs will be used to supply Level1 trigger inputs; however some
parts may be reused if some FASTBUS Lecroy 1881 ADC boards will stay
¥existing Level1 trigger system
(accepts data from pretrigger system, process them with 15ns strob and generates decision in
100ns timeframe) will be replaces with new system with similar timing parameters
but more powerful and flexible logic and inputs from both existing
pretriggers and FADCs
¥Level2 trigger system (accepts data
from Level1 and trackers and generates decision in 4us timeframe) will be replaced by
new more selective system
¥level3 'trigger' (software component
running on SMP) will be reused; new event- and data-reduction algorithms will be developed
and processed in that component; 8-CPU machine will be sufficient,
no farm system is planed