CLAS DAQ UPGRADE
(lehman2006)

Progress since 2005


	All FASTBUS and VME Readout Controllers were equipped with secondary CPUs to increase performance; that configuration will be used in CLAS12
	CLAS Online cluster upgrade was completed including new network equipment, new servers and new RAID system; some of those will be used in CLAS12
	CODA software was redesign to accommodate new hardware and improve performance; those changes will be included in new version of CODA for CLAS12
	Event rate 8kHz was achieved at data rate 30MB/sec and dead time less the 15% which is significant step to 12GeV requirements

Slide 3

Overview: Trigger System


	- existing pretrigger system (CAMAC- and VME/VXI-based discriminators accepting data from scintillator-based detectors and producing signals for Level1 logic) will be removed completely if FADCs will be used to supply Level1 trigger inputs; however some parts may be reused if some FASTBUS Lecroy 1881 ADC boards will stay
	existing Level1 trigger system (accepts data from pretrigger system, process them with 15ns strob and generates decision in 100ns timeframe) will be replaces with new system with similar timing parameters but more powerful and flexible logic and inputs from both existing pretriggers and FADCs
	Level2 trigger system (accepts data from Level1 and trackers and generates decision in 4us timeframe) will be replaced by new more selective system
	level3 'trigger' (software component running on SMP) will be reused; new event- and data-reduction algorithms will be developed and processed in that component; 8-CPU machine will be sufficient, no farm system is planed

Overview: Front End System


	digitizing electronics (VME pipeline TDCs and scalers, FASTBUS ADCs and multihit TDCs) will be upgraded; VME electronics will stay; FASTBUS ADCs will be replaced by FADCs at least partially; FASTBUS multihit TDCs will stay but replacement solution will be provided in case of aging problems
	front-end readout (28 crates with PowerPC-based Motorola VME multi-CPU controllers) will be reused; some hardware upgrades and software improvements are required; the number of crates will be increased up to about 40

Overview: Back End System


	event building system (QUAD SMP and corresponding software supporting multiprocessor and multithreaded environment) will be upgraded; new event building will be performed in 2 stages: 7 builders at first stage (6 sectors and central detectors) and final building at second stage; QUAD- or 8-CPU-machines similar to existing one will be sufficient; software development is required to support multistage building
	event recording system (QUAD SMP, RAID system and corresponding software) will be reused or upgraded if necessary
	networking system: some improvements will be done to increase bandwidth and the number of clients

Overview: Monitoring


	hardware control and monitoring (mostly EPICS-based system, some standalone components) will be reused; standalone components will be included in EPICS
	data monitoring (full event reconstruction is running online; raw and reconstructed data is presented in several visualization programs) will be reused; new event processing algorithms will be developed in frame of offline project and incorporated into online environment; hardware and data monitoring will be combined together in one generic system to provide precise diagnostics (Experiment Control System)
	event display (visually presents CLAS detectors) will be reused; new detector components will be added
	online calibration system will be created to provide information for both online and offline data processing

Requirements and Key Features


	10kHz event rate, 100MBytes/s data rate, <15% dead time
	system includes existing and new hardware and software components
	35,000 channels of ADCs and TDCs
	40 crates of VME/VME64X and FASTBUS with future FASTBUS replacement
	flexible event triggering and data filtering system
	Experiment Control System including run control and powerful monitoring

Cost table

Obligation and Labor Profile

Critical Path Chart

Critical Path Description


	we are confident that required DAQ performance (10KHz and 100MB/sec at dead time <15%) will be achieved just by using new computer technologies available on market
	it is important to increase a portion of 'good' data in data stream, so main efforts in 2006-2008 will be spent on Level1 trigger and Flash ADC projects
	all hardware components design will be completed in 2008
	software development will be performed during 2005-2010 period
	main hardware purchases will be made in 2011

Contingency Analysis


	FADCs price per channel $120 must be considered as the main contingency. Currently available boards costs about $500 per channel. We assume that price will go down by 2011, and home-made FADCs are considered as an option. All other hardware components have catalog price.

Key Milestone Summary


	finish all components design by 2008
	Level 1 trigger system prototype build and tested in CLAS by 2008, ready by 2009
	FADCs sample units tested in CLAS by 2008
	all software completion by 2010
	whole system completion in 2011

Risk Analysis

FY07 plan: Trigger System



	a) Trigger System Conceptual design (physics level)
	manpower: scientist
	duration: 3 month
	predecessors: none
	work description: evaluate current Trigger System and its limitations; make a list of new components which can improve a trigger system; present the list of proposed components as a combination of level1 and level2 subsystems communicating to each other; include both existing and proposed detectors into the system

	b) Trigger System simulation, Level 1 (physics level)
	manpower: scientist
	duration: 3 month
	predecessors: (a)
	work description: study the efficiency of proposed components based on CLAS data analysis for existing detectors and simulation results for proposed CLAS12 detectors (if available); the list of components must include cluster finding in calorimeters and matching between different detectors incorporated into Level 1 trigger logic; fixed execution time must be provided for any trigger component; make final list of components which should be included into CLAS12 Level 1 trigger system

FY07 plan: Trigger System (cont.)


	c) Trigger System simulation, Level 2 (physics level)
	manpower: scientist
	duration: 6 month
	predecessors: (a)
	work description: study the efficiency of proposed components based on CLAS data analysis for existing detectors and simulation results for proposed CLAS12 detectors (if available); the list of components must include segment finding and road finding in tracking detectors, as well as matching of level1 and level2 outputs; fixed execution time must be provided for any trigger component; make final list of components which should be included into CLAS12 Level 2 trigger system

	d) Trigger System Technical design (electronics level)
	manpower: scientist, electronic engineer
	duration: 3 month
	predecessors: (b)(c)
	work description: study the possibility of implementation of the proposed trigger components on electronic level; redesign proposed algorithms if necessary to make them suitable for available electronics; analyze FADC sums and tracking detectors output requirements; present the first version of CLAS12 Trigger System Technical design

FY07 plan: Flash ADC studies


	a) FADC boards studies
	manpower: contract scientist
	duration: 6 month
	predecessors: none
	work description: install and study Struck SIS3320 FADC board (12bit 200MHz 2eSST readout) in test setup and in Hall B; obtain data from CLAS detectors and compare them with Lecroy 1881M data; provide all necessary software libraries; study other FADC boards if available

	b) FADC data analysis
	manpower: scientist
	duration: 3 month
	predecessors: (a)
	work description: analyze FADC data offline; make decisions on data format and data processing algorithms, including recommendations for FADC sums output

FY07 plan: summary