| CLAS DAQ UPGRADE (lehman2005) |
| Sergey Boyarinov | |
| July 2005 | |
| TJNAF |
| Overview: Trigger System |
| - existing pretrigger system (CAMAC- and VME/VXI-based discriminators accepting data from scintillator-based detectors and producing signals for Level1 logic) will be removed completely if FADCs will be used to supply Level1 trigger inputs; however some parts may be reused if some FASTBUS Lecroy 1881 ADC boards will stay | |
| existing Level1 trigger system (accepts data from pretrigger system, process them with 15ns strob and generates decision in 100ns timeframe) will be replaces with new system with similar timing parameters but more powerful and flexible logic and inputs from both existing pretriggers and FADCs | |
| Level2 trigger system (accepts data from Level1 and trackers and generates decision in 4us timeframe) will be removed or optionally replaced by new more selective system | |
| level3 'trigger' (software component running on SMP) will be reused; new event- and data-reduction algorithms will be developed and processed in that component; 8-CPU machine will be sufficient, no farm system is planed |
| Overview: Front End System |
| digitizing electronics (VME pipeline TDCs and scalers, FASTBUS ADCs and multihit TDCs) will be upgraded; VME electronics will stay; FASTBUS ADCs will be replaced by FADCs at least partially; FASTBUS multihit TDCs will stay but replacement solution will be provided in case of aging problems | |
| front-end readout (28 crates with PowerPC-based Motorola VME multi-CPU controllers) will be reused; some hardware upgrades and software improvements are required; the number of crates will be increased up to about 40 |
| Overview: Back End System |
| event building system (QUAD Opteron-based machine and corresponding software supporting multiprocessor and multithreaded environment) will be upgraded; new event building will be performed in 2 stages: 7 builders at first stage (6 sectors and central detectors) and final building at second stage; QUAD- or 8-CPU-machines similar to existing one will be sufficient; software development is required to support multistage building | |
| event recording system (SUN Sparc SMP, RAID system and corresponding software) will be replaced by faster machine and disks to process increased data rate | |
| networking system: some improvements will be done to increase bandwidth and the number of clients |
| Overview: Monitoring |
| hardware control and monitoring (mostly EPICS-based system, some standalone components) will be reused; standalone components will be included in EPICS | |
| data monitoring (full event reconstruction is running online; raw and reconstructed data is presented in several visualization programs) will be reused; new event processing algorithms will be developed in frame of offline project and incorporated into online environment; hardware and data monitoring will be combined together in one generic system to provide precise diagnostics | |
| event display (visually presents CLAS detectors) will be reused; new detector components will be added | |
| online calibration system will be created to provide information for both online and offline data processing |
| Requirements and Key Features |
| 10kHz event rate, 100MBytes/s data rate, <15% dead time | |
| system includes existing and new hardware and software components | |
| 35,000 channels of ADCs and TDCs | |
| 40 crates of VME/VME64X and FASTBUS with future FASTBUS replacement | |
| flexible event triggering and data filtering system | |
| powerful monitoring system including combined hardware and data control |
| Cost table |
| Obligation and Labor Profile |
| Critical Path Chart |
| Critical Path Description |
| all hardware components desing will be completed in 2008 | |
| main efforts in 2006-2008 will be spent on Level1 trigger and FADCs projects | |
| software development will be performed during 2005-2010 period | |
| main hardware purchases will be made in 2011 |
| Contingency Analysis |
| FADCs price per channel $120 must be considered as the main contingency. Currently available boards costs about $500 per channel. We assume that price will go down by 2011, and home-made FADCs are considered as an option. All other hardware components have catalog price. |
| Key Milestone Summary |
| finish all components design by 2008 | |
| Level 1 trigger system prototype build and tested in CLAS by 2008, ready by 2009 | |
| FADCs sample units tested in CLAS by 2008 | |
| all software completion by 2010 | |
| whole system completion in 2011 |
| Risk Analysis |
| Slide 14 |