| Upgrading CLAS DAQ for High Luminosities |
| Sergey Boyarinov | |
| JLAB Science and Technology Review | |
| July 12-14, 2006 |
| Data Volume per experiment
per year (Raw data) |
| Motivation |
| Recent CLAS experiments (EG3, DVCS, EG4 etc) requires higher event rate (up to 8kHz) and data rate (up to 35MB/s) | |
| Improved DAQ performance gives an advantage for upcoming CLAS experiments (FROST, DVCS-II etc) | |
| Increasing luminosity to >1035cm-2s-1 for CLAS12 requires DAQ running at event rate 10kHz and data rate 100MB/sec | |
| New solutions available (pipeline TDCs, VME Readout Controller multiprocessing, new computer/network equipment) |
| Goals for CLAS DAQ upgrades |
| At least 10kHz event rate | |
| At least 50MB/sec data rate | |
| Less then 15% dead time | |
| Driven mostly by EG3 experiment requirements (8kHz, 35MB/s) with 25% margin |
| Slide 5 |
| 1. New pipeline TDCs |
| Main goal: decrease CLAS dead time | |
| Method: use dead-timeless boards | |
| All FASTBUS TDCs were replaced by pipeline TDCs with appropriate resolution: 26 CAEN v1190 boards, 8 CAEN v1290 boards and 14 F1TDC boards were installed | |
| CLAS time-of-flight, forward calorimeter, large angle calorimeter, Cherenkov counter, start counter and tagger systems were equipped with 3000 channels of pipeline TDCs | |
| New TDC trigger and TDC reference systems were installed | |
| TDC calibration system was updated | |
| Readout and calibration software were developed |
| Slide 7 |
| DAQ improvement by using pipeline TDCs |
| CLAS dead time decreased from 35-40 microsec variable to 12 microsec fixed (now defined by CLAS ADC boards) making it possible to achieve 10kHz event rate at dead time below 15% | |
| 2. VME Readout Controllers Upgrade |
| Main goal: increase DAQ event rate limit | |
| Method: multi-processing | |
| 10 PrPMC880s and 17 PMC280s Motorola co-processor boards were configured to work with all CLAS VME Motorola controllers: mv2306/mv3432/mv5100/mv5500/mv6100 | |
| VXWORKS support for dual-CPU systems was provided: Motorola Board Support Packages were modified | |
| Most of CLAS Front-End VME controllers were equipped with co-processor boards | |
| CLAS DAQ software was modified to utilize dual-CPU Readout Controllers |
| Slide 10 |
| DAQ improvement by using dual-CPU ROCs |
| CLAS DAQ event rate limit was increased from 3kHz to 8kHz with the possibility of future improvements | |
| 3. Network and UNIX cluster Upgrade |
| Main goal: increase DAQ data rate limit | |
| Method: faster computing, multi-processing | |
| New GBit network equipment | |
| 3 new QUAD Opteron-based UNIX servers running Solaris and Linux | |
| New RAID system | |
| New Event Builder software with multi-threaded building part | |
| Slide 13 |
| Slide 14 |
| DAQ improvement by upgrading UNIX cluster |
| CLAS DAQ data rate limit was increased from 17MB/s up to at least 35MB/s | |
| Data rate reached 50MB/s during non-beam test, not yet tested in real experiment |
| Slide 16 |
| Conclusion |
| CLAS DAQ performance was improved significantly: event rate increased from 3kHz to 8kHz, data rate from 17MB/s to at least 50MB/s, dead time remains below 15% | |
| Event rate will reach 10kHz after pipeline TDCs readout speed will be increased by using 2eVME protocol - CAEN is working on new firmware | |
| Free-running front-end and multiprocessing back-end were two key technologies used in upgrade | |
| Total project cost: hardware about $600K, manpower about 3 years | |
| DAQ upgrade allows much more efficient running of upcoming CLAS experiments | |
| Big step to meet CLAS12 requirements | |
| Data Volume per experiment
per year (Raw data) |