CLAS DAQ upgrade


	Part1: pipeline TDCs

	S.Boyarinov, S.Pozdnyakov, V.Sapunenko
	(CLAS online)

	D. Abbott (CODA)

	J.Langheinrich (CLAS offline)

Why to replace 1872s/1875s ?


	Big conversion time: 10usec+2.5usec/hit is main contributor to CLAS front end busy time
	Conversion time depends on occupancy
	Slow readout: block readout is not supported; all remaining FASTBUS boards in CLAS support 64-bit single block readout
	There is no headers in output data: slower data processing
	ÒCommon startÓ mode only; delay cables are needed
	Maintenance problems

Goals


	Decrease CLAS front end busy time from variable 35-40us (electron runs) and 50us (photon runs) to fixed 12us
	Make it possible to increase event rate for entire CLAS up to 10kHz at dead time below 15%
	Higher time resolution where necessary (T-counters for instance)
	Multiple hits per TDC channel (important for high-loaded detectors)

Available pipeline TDC boards

Main pipeline TDC parameters
(company specs)

Project in numbers


	5 new VME64X crates in Hall and 1 VME64X crate in test setup, all remotely controlled over ethernet using SNMP protocol or HTTP
	26 v1190 boards, 8 v1290 boards, 14 F1TDC boards
	80 cables equipped with high-dense 68-pin connectors were produced and installed
	About 3000 channels used by time-of-flight, forward calorimeter, large angle calorimeter, cherenkov counter, start counter and tagger systems
	New TDC trigger and TDC reference systems
	Updated TDC calibration system
	Overall cost over $300k

TDC trigger system


	Use Level 2 PASS signal from Trigger Supervisor: works for both Level1 and Level2 trigger modes
	V1190/v1290: desy-chained NIM signal
	F1TDC: signal distribution system (VME back-mounted distribution board and one daughter board per TDC)

TDC reference signals


	There is no external synchronized clock, every board is running from its internal clock
	First channel in every TDC board has L1ACCEPT signal used as reference
	Reference hit recognized and subtracted during translation procedure in second readout list; reference hit presence is checked at that time

TDC calibration


	To be added

TDC readout


	V1190/v1290: event-by-event 64bit chained DMA; VME64X backplanes were modified
	F1TDC: event-by-event 64bit DMA
	Data rate about 30MB/sec
	TDC window position and size are programmable and defined in first readout list
	New data banks were implemented to support multihit format

Project timeline (CAEN TDCs)


	Decision to replace FASTBUS 1872/1875 boards: July 2002
	Overall design, TDC market studies, sample boards testing: summer 2002-summer 2003
	Requisitions for TDCs: July 2003
	Software development: 2002-2004
	VME64X crates installation: November 2003
	Project rescheduled to meet EG3 run demands; completion date set to November 2004: January 2004
	First two TDCs received and tested: February 2004
	TDCs complete delivery: March 2004
	TDCs test setup studies: April-June 2004
	TDCs installation started: July 2004
	TDCs system full assembly: September 2004
	TDCs calibration: October-November 2004
	TDCs system is operational: November 2004
	TDCs used in real run (EG3): starting November 25, 2004

Project timeline (F1TDCs)


	Decision to use F1TDCs for Time-Of-Flight system: July 2003
	Requisition: September 2003
	Software development: 2003-2004
	Project rescheduled to meet EG3 run demands; completion date set to November 2004: January 2004
	First 5 boards and temporary distribution board delivery: July 2004
	Decision to use F1TDCs not in Time-Of-Flight system but in Large Angle Calorimeter because of lack of time: October 2004
	Full delivery including signal distribution boards: Nov 17, 2004
	System is working in test setup: Nov 24, 2004
	Project postponed because of EG3 run started Nov 25; work was resumed after EG3
	System is operational, all boards are installed in Large Angle Calorimeter in low resolution mode: March 2005
	TDCs used in real run (DVCS): starting March 23, 2005

Conclusion


	All high-resolution TDCs in CLAS are pipeline multihit boards
	CLAS front-end busy is fixed 12us (defined by Lecroy 1881 ADCs) which makes it possible to increase event rate up to 10kHz at dead time below 15%
	In general we were satisfied with service provided by commercial companies: WIENER service (VME64X crates) was very good; CEAN service was good but several iterations of sample boards and firmwire upgrades were needed to get required parameters; following support from both companies was very good
	Better coordination is required in future to keep our schedule in sync with other Hall B and JLAB groups

References

Acknowledgments