Level 1, Stage 1: FADC board, 4ns event clock
16 inputs, each input
produces ADC
value every 4ns
ADCs (up to 16x4bit):
up to 8 bytes total
select hits with ADCs
above threshold[0];
produces
list of 4-bit
ADC
values
NOTE: 10GBit link can transfer 8bytes
in 8ns, so following processing
units may have 8ns event clock;
BUT: average number will be less, so
buffering and/or compressing should help