Calorimeters, TOFs, CherenkovÕs
pipe
pipe
FPGA
ÉÉ.
16 ch FADC
ÉÉ.
Bit pattern (16bit)
Energy sum (16bit)
Crate
Level
Processing
Unit
(from
16 FADC
boards:
up to
256
channels)
Level
1 Processor
(from
16+ crates)
Clusters
Energy sum
Every 4ns
Level
2 Processor
(new segment finders
in ADB crates,
new sector-based
Road finders)
Final
Event
Processor
Drift
Chambers (hits)
Level1
10GBit link