https://clonwiki0.jlab.org/wiki/api.php?action=feedcontributions&feedformat=atom&user=129.57.32.67 2026-04-09T13:20:53Z User contributions MediaWiki 1.42.1 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3289 2008-03-26T14:53:57Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski, Ivan Bedlinski, Pawel Turonski, Benjamin Raydo, Eugene Pasyuk, Sergey Pozdnyakov<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel developed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2<br /> <br /> System is in commissioning right now, EPICS part still under development; full system testing will be conducted during 3 following days.<br /> Windows GUI produces file to be downloaded by scripts, upload command is exist as well.<br /> <br /> Electron trigger to be reconfigured to bit 9, plugging rendom pulser to old L1 sync. MOR must goto sync as well.<br /> <br /> Print (to clonhp or file) from clonwin2 to be done using screen snapshot (need to make sure clonwin2 mounts fileserver and connected to printers).<br /> <br /> ECL outputs from ORs will goto old level1, as well as outputs from ST to implement neutral trigger. We may need bit 8 as well for electron trigger (old level1), then we have to disconnect it from new level1,<br /> <br /> We'll start from 2 electron triggers on bit 9, and decide on bit 8 later, after taking some data.<br /> <br /> Preliminary tests shows that new level1 faster then old one in about 25ns.<br /> <br /> Check why spike in TDC spectra around 4000.<br /> <br /> Level1 testing plan:<br /> <br /> * setting ST in old position<br /> * make sure TOF coincides with ST<br /> * align ST between themselfs; may need delay boards, existing is broken (left one, channel 0), also have 2ns, need 1ns<br /> * procedure will be repeated with beam<br /> <br /> Delay curve script under development by Valeri and Ivan.<br /> <br /> <br /> 2. Trigger files for both level1's.<br /> <br /> Need 2 syncs, lets use 3 and 4 (EP outputs 5-8).<br /> Sergey will make appropriate cabling and config files.</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3288 2008-03-26T14:47:20Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski, Ivan Bedlinski, Pawel Turonski, Benjamin Raydo, Eugene Pasyuk, Sergey Pozdnyakov<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel developed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2<br /> <br /> System is in commissioning right now, EPICS part still under development; full system testing will be conducted during 3 following days.<br /> Windows GUI produces file to be downloaded by scripts, upload command is exist as well.<br /> <br /> Electron trigger to be reconfigured to bit 9, plugging rendom pulser to old L1 sync. MOR must goto sync as well.<br /> <br /> Print (to clonhp or file) from clonwin2 to be done using screen snapshot (need to make sure clonwin2 mounts fileserver and connected to printers).<br /> <br /> ECL outputs from ORs will goto old level1, as well as outputs from ST to implement neutral trigger. We may need bit 8 as well for electron trigger (old level1), then we have to disconnect it from new level1,<br /> <br /> We'll start from 2 electron triggers on bit 9, and decide on bit 8 later, after taking some data.<br /> <br /> Preliminary tests shows that new level1 faster then old one in about 25ns.<br /> <br /> Check why spike in TDC spectra around 4000.<br /> <br /> Level1 testing plan:<br /> <br /> * setting ST in old position<br /> * make sure TOF coincides with ST<br /> * align ST between themselfs; may need delay boards, existing is broken (left one, channel 0), also have 2ns, need 1ns<br /> * procedure will be repeated with beam<br /> <br /> Delay curve script under development by Valeri and Ivan.<br /> <br /> <br /> 2.</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3287 2008-03-26T14:46:15Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski, Ivan Bedlinski, Pawel Turonski, Benjamin Raydo, Eugene Pasyuk, Sergey Pozdnyakov<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel developed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2<br /> <br /> System is in commissioning right now, EPICS part still under development; full system testing will be conducted during 3 following days.<br /> Windows GUI produces file to be downloaded by scripts, upload command is exist as well.<br /> <br /> Electron trigger to be reconfigured to bit 9, plugging rendom pulser to old L1 sync. MOR must goto sync as well.<br /> <br /> Print (to clonhp or file) from clonwin2 to be done using screen snapshot (need to make sure clonwin2 mounts fileserver and connected to printers).<br /> <br /> ECL outputs from ORs will goto old level1, as well as outputs from ST to implement neutral trigger. We may need bit 8 as well for electron trigger (old level1), then we have to disconnect it from new level1,<br /> <br /> We'll start from 2 electron triggers on bit 9, and decide on bit 8 later, after taking some data.<br /> <br /> Preliminary tests shows that new level1 faster then old one in about 25ns.<br /> <br /> Check why spike in TDC spectra around 4000.<br /> <br /> Level1 testing plan:<br /> <br /> * setting ST in old position<br /> * make sure TOF coincides with ST<br /> * align ST between themselfs; may need delay boards, existing is broken (left one, channel 0), also have 2ns, need 1ns<br /> * procedure will be repeated with beam</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3286 2008-03-26T14:45:46Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski, Ivan Bedlinski, Pawel Turonski, Benjamin Raydo, Eugene Pasyuk, Sergey Pozdnyakov<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel developed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2<br /> <br /> System is in commissioning right now, EPICS part still under development; full system testing will be conducted during 3 following days.<br /> Windows GUI produces file to be downloaded by scripts, upload command is exist as well.<br /> <br /> Electron trigger to be reconfigured to bit 9, plugging rendom pulser to old L1 sync. MOR must goto sync as well.<br /> <br /> Print (to clonhp or file) from clonwin2 to be done using screen snapshot (need to make sure clonwin2 mounts fileserver and connected to printers).<br /> <br /> ECL outputs from ORs will goto old level1, as well as outputs from ST to implement neutral trigger. We may need bit 8 as well for electron trigger (old level1), then we have to disconnect it from new level1,<br /> <br /> We'll start from 2 electron triggers on bit 9, and decide on bit 8 later, after taking some data.<br /> <br /> Preliminary tests shows that new level1 faster then old one in about 25ns.<br /> <br /> Check why spike in TDC spectra around 4000.<br /> <br /> Level1 testing plan:<br /> <br /> * setting ST in old position<br /> * make sure TOF coincides with ST<br /> * align ST between themselfs; may need delay boards, existing is broken (left one, channel 0)<br /> * procedure will be repeated with beam</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3285 2008-03-26T14:29:20Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski, Ivan Bedlinski, Pawel Turonski, Benjamin Raydo, Eugene Pasyuk, Sergey Pozdnyakov<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel developed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2<br /> <br /> System is in commissioning right now, EPICS part still under development; full system testing will be conducted during 3 following days.<br /> Windows GUI produces file to be downloaded by scripts, upload command is exist as well.<br /> <br /> Electron trigger to be reconfigured to bit 9, plugging rendom pulser to old L1 sync. MOR must goto sync as well.<br /> <br /> Print (to clonhp or file) from clonwin2 to be done using screen snapshot (need to make sure clonwin2 mounts fileserver and connected to printers).<br /> <br /> ECL outputs from ORs will goto old level1, as well as outputs from ST to implement neutral trigger. We may need bit 8 as well for electron trigger (old level1), then we have to disconnect it from new level1,<br /> <br /> We'll start from 2 electron triggers on bit 9, and decide on bit 8 later, after taking some data.<br /> <br /> Preliminary tests shows that new level1 faster then old one in about 25ns.</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3284 2008-03-26T14:27:33Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski, Ivan Bedlinski, Pawel Turonski, Benjamin Raydo, Eugene Pasyuk, Sergey Pozdnyakov<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel developed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2<br /> <br /> System is in commissioning right now, EPICS part still under development; full system testing will be conducted during 3 following days.<br /> Windows GUI produces file to be downloaded by scripts, upload command is exist as well.<br /> <br /> Electron trigger to be reconfigured to bit 9, plugging rendom pulser to old L1 sync. MOR must goto sync as well.<br /> <br /> Print (to clonhp or file) from clonwin2 to be done using screen snapshot (need to make sure clonwin2 mounts fileserver and connected to printers).<br /> <br /> ECL outputs from ORs will goto old level1, as well as outputs from ST to implement neutral trigger. We may need bit 8 as well for electron trigger (old level1), then we have to disconnect it from new level1,<br /> <br /> We'll start from 2 electron triggers on bit 9, and decide on bit 8 later, after taking some data.</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3283 2008-03-26T14:25:16Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski, Ivan Bedlinski, Pawel Turonski, Benjamin Raydo, Eugene Pasyuk, Sergey Pozdnyakov<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel developed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2<br /> <br /> System is in commissioning right now, EPICS part still under development; full system testing will be conducted during 3 following days.<br /> Windows GUI produces file to be downloaded by scripts, upload command is exist as well.<br /> <br /> Electron trigger to be reconfigured to bit 9, plugging rendom pulser to old L1 sync. MOR must goto sync as well.<br /> <br /> Print (to clonhp or file) from clonwin2 to be done using screen snapshot. <br /> ECL outputs from ORs will goto old level1, as well as outputs from ST to implement neutral trigger. We may need bit 8 as well for electron trigger (old level1), then we have to disconnect it from new level1,<br /> <br /> We'll start from 2 electron triggers on bit 9, and decide on bit 8 later, after taking some data.</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3282 2008-03-26T14:24:52Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski, Ivan Bedlinski, Pawel Turonski, Eugene Pasyuk, Sergey Pozdnyakov<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel developed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2<br /> <br /> System is in commissioning right now, EPICS part still under development; full system testing will be conducted during 3 following days.<br /> Windows GUI produces file to be downloaded by scripts, upload command is exist as well.<br /> <br /> Electron trigger to be reconfigured to bit 9, plugging rendom pulser to old L1 sync. MOR must goto sync as well.<br /> <br /> Print (to clonhp or file) from clonwin2 to be done using screen snapshot. <br /> ECL outputs from ORs will goto old level1, as well as outputs from ST to implement neutral trigger. We may need bit 8 as well for electron trigger (old level1), then we have to disconnect it from new level1,<br /> <br /> We'll start from 2 electron triggers on bit 9, and decide on bit 8 later, after taking some data.</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3281 2008-03-26T14:10:16Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski, Ivan Bedlinski, Pawel Turonski, Eugene Pasyuk, Sergey Pozdnyakov<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel developed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2<br /> <br /> System is in commissioning right now, EPICS part still under development; full system testing will be conducted during 3 following days.<br /> Windows GUI produces file to be downloaded by scripts, upload command is exist as well.<br /> <br /> Electron trigger to be reconfigured to bit 9, plugging rendom pulser to old L1 sync. MOR must goto sync as well.</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3280 2008-03-26T14:09:53Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski, Ivan Bedlinski, Pawel Turonski<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel developed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2<br /> <br /> System is in commissioning right now, EPICS part still under development; full system testing will be conducted during 3 following days.<br /> Windows GUI produces file to be downloaded by scripts, upload command is exist as well.<br /> <br /> Electron trigger to be reconfigured to bit 9, plugging rendom pulser to old L1 sync. MOR must goto sync as well.</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3279 2008-03-26T14:02:33Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski, Ivan Bedlinski, Pawel Turonski<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel developed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2<br /> <br /> System is in commissioning right now, EPICS part still under development; full system testing will be conducted during 3 following days.<br /> Windows GUI will produce</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3278 2008-03-26T13:52:09Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski,<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel developed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2<br /> <br /> System is in commissioning right now, EPICS part still under development; full system testing will be conducted during 3 following days</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3277 2008-03-26T13:50:17Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski,<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel developed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3276 2008-03-26T13:49:55Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski,<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector (Sergey B.)<br /> <br /> * Valeri and Pavel designed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3275 2008-03-26T13:49:25Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski,<br /> <br /> 1. New level1 trigger system has been installed; it includes following components:<br /> <br /> * clastrig2: CAEN v1495 logic unit with 2 daughter cards: 8 NIM input card and 32 ECL output card<br /> <br /> * sc2: 6 OR modules<br /> <br /> * outputs from TOF and ST pretrigger discriminators were rerouted to the v1495 board: ST directly, TOF through OR modules making OR of all channels in one sector<br /> <br /> * Valeri and Pavel designed the photon level 1 trigger logic diagram<br /> <br /> * Ben programmed v1495 module with desired logic and produced Windows-based GUI to control the logic<br /> <br /> * Sergey B. developed vxWorks-side supporting library including tcp server to support Windows-vxWorks communication<br /> <br /> * Sergey B., Nerses and Hovanes implemented EPICS support for the new electronics, including ioc in clastrig2</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_26,_2008_online_meeting_minutes&diff=3274 2008-03-26T13:40:32Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Valeri Koubarovski,</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=CLON_meeting_March_26,_2008&diff=3273 2008-03-26T13:34:11Z

<p>129.57.32.67: </p> <hr /> <div>Clas On-line Meeting, Wednesday, March 26 at 10am in Room A110<br /> ------------------------------------------------------------------<br /> <br /> 1. G12 preparations<br /> <br /> * new level1 trigger<br /> <br /> * ???</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=CLON_Group_Meetings&diff=3272 2008-03-26T13:33:24Z

<p>129.57.32.67: </p> <hr /> <div>[[CLON meeting December 13, 2006]] &gt;&gt;&gt;&gt;&gt; [[December 13, 2006 online meeting minutes]]<br /> <br /> ==== 2007<br /> <br /> [[CLON meeting September 5, 2007]] &gt;&gt;&gt;&gt;&gt; [[September 5, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting September 12, 2007]] &gt;&gt;&gt;&gt;&gt; [[September 12, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting September 19, 2007]] &gt;&gt;&gt;&gt;&gt; [[September 19, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting September 26, 2007]] &gt;&gt;&gt;&gt;&gt; [[September 26, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting October 3, 2007]] &gt;&gt;&gt;&gt;&gt; [[October 3, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting October 10, 2007]] &gt;&gt;&gt;&gt;&gt; [[October 10, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting October 17, 2007]] &gt;&gt;&gt;&gt;&gt; [[October 17, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting October 24, 2007]] &gt;&gt;&gt;&gt;&gt; [[October 24, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting October 31, 2007]] &gt;&gt;&gt;&gt;&gt; [[October 31, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting November 7, 2007]] &gt;&gt;&gt;&gt;&gt; [[November 7, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting November 14, 2007]] &gt;&gt;&gt;&gt;&gt; [[November 14, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting November 28, 2007]] &gt;&gt;&gt;&gt;&gt; [[November 28, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting December 12, 2007]] &gt;&gt;&gt;&gt;&gt; [[December 12, 2007 online meeting minutes]]<br /> <br /> ==== 2008<br /> <br /> [[CLON meeting January 16, 2008]] &gt;&gt;&gt;&gt;&gt; [[January 16, 2008 online meeting minutes]]<br /> <br /> [[CLON meeting January 23, 2008]] &gt;&gt;&gt;&gt;&gt; [[January 23, 2008 online meeting minutes]]<br /> <br /> [[CLON meeting January 30, 2008]] &gt;&gt;&gt;&gt;&gt; [[January 30, 2008 online meeting minutes]]<br /> <br /> [[CLON meeting February 13, 2008]] &gt;&gt;&gt;&gt;&gt; [[February 13, 2008 online meeting minutes]]<br /> <br /> [[CLON meeting March 5, 2008]] &gt;&gt;&gt;&gt;&gt; [[March 5, 2008 online meeting minutes]]<br /> <br /> [[CLON meeting March 12, 2008]] &gt;&gt;&gt;&gt;&gt; [[March 12, 2008 online meeting minutes]]<br /> <br /> [[CLON meeting March 26, 2008]] &gt;&gt;&gt;&gt;&gt; [[March 26, 2008 online meeting minutes]]</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=Scratch&diff=3270 2008-03-14T15:53:41Z

<p>129.57.32.67: </p> <hr /> <div>CLAS12 DC (Mac 14-nov-2007): 2 stereo, +-6 degrees, good resolution (1% dp/p, 1 mrad angle), six 6-layer superlayers, 112 wires per layer; reconstruction improvements: use double hits, use segment angle in road dictionary, early l-r ambig. resolution (now it resolved locally and then corrected after track reconstructed ?), find tracks with no TOF hit and cut off accidental tracks (using residials ?), derive off-diagonal terms in error matrix<br /> <br /> <br /> SVT readout:<br /> <br /> SVX4 - old chip<br /> 132ns clock, 40pipeline cells -&gt;5.2us trigger latency; can select readout window like pipeline TDCs (position defined +-132us, window size 132ns fixed)<br /> initial part stored upto 4 events, they are rotating internally<br /> 32 bits per hit, 128 channels per chip, ... -&gt; 3.2us per chip to get data from the chip to the buffer of 512 full events<br /> L2 pipeline 16us<br /> L1 latency from Amrit is 3us, Amrit will try to make it 4us<br /> Use the same clock as entire CLAS12 trigger system (256MHz)<br /> <br /> FSSR 125ns instead of 132ns (built for BTev, never used)<br /> self-triggering, do not need L1ACCEPT, L2 pipe 16us can be implemented<br /> <br /> SVX4 goes to review !!!<br /> <br /> Generic DAQ drawing will be sent to Amrit in April</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=Scratch&diff=3269 2008-03-14T15:51:09Z

<p>129.57.32.67: </p> <hr /> <div>CLAS12 DC (Mac 14-nov-2007): 2 stereo, +-6 degrees, good resolution (1% dp/p, 1 mrad angle), six 6-layer superlayers, 112 wires per layer; reconstruction improvements: use double hits, use segment angle in road dictionary, early l-r ambig. resolution (now it resolved locally and then corrected after track reconstructed ?), find tracks with no TOF hit and cut off accidental tracks (using residials ?), derive off-diagonal terms in error matrix<br /> <br /> <br /> SVT readout:<br /> <br /> SVX4 - old chip<br /> 132ns clock, 40pipeline cells -&gt;5.2us trigger latency; can select readout window like pipeline TDCs (position defined +-132us, window size 132ns fixed)<br /> initial part stored upto 4 events, they are rotating internally<br /> 32 bits per hit, 128 channels per chip, ... -&gt; 3.2us per chip to get data from the chip to the buffer of 512 full events<br /> L2 pipeline 16us<br /> L1 latency from Amrit is 3us, Amrit will try to make it 4us<br /> Use the same clock as entire CLAS12 trigger system (256MHz)<br /> <br /> FSSR 125ns instead of 132ns (built for BTev, never used)<br /> self-triggering, do not need L1ACCEPT, L2 pipe 16us can be implemented<br /> <br /> SVX4 goes to review !!!</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=Scratch&diff=3268 2008-03-14T15:25:58Z

<p>129.57.32.67: </p> <hr /> <div>CLAS12 DC (Mac 14-nov-2007): 2 stereo, +-6 degrees, good resolution (1% dp/p, 1 mrad angle), six 6-layer superlayers, 112 wires per layer; reconstruction improvements: use double hits, use segment angle in road dictionary, early l-r ambig. resolution (now it resolved locally and then corrected after track reconstructed ?), find tracks with no TOF hit and cut off accidental tracks (using residials ?), derive off-diagonal terms in error matrix<br /> <br /> <br /> SVT readout:<br /> <br /> SVX4 - old chip<br /> 132ns clock, 40pipeline cells -&gt;5.2us trigger latency; can select readout window like pipeline TDCs (position defined +-132us, window size 132ns fixed)<br /> initial part stored upto 4 events, they are rotating internally<br /> 32 bits per hit, 128 channels per chip, ... -&gt; 3.2us per chip to get data from the chip to the buffer of 512 full events<br /> L2 pipeline 16us<br /> L1 latency from Amrit is 3us, Amrit will try to make it 4us<br /> <br /> FSSR 125ns instead of 132ns</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_12,_2008_online_meeting_minutes&diff=3267 2008-03-12T15:16:17Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Ben Raydo, Sergey Pozdnyakov, Raffaella Devita, Valeri Kubarovski<br /> <br /> 1. G12 trigger<br /> <br /> * do not destroy existing trigger<br /> <br /> * new VME crate on top of trigger rack, all OR modules there, VME repeater<br /> <br /> * about 50 scalers, 2 reads by 16bit, every 10 seconds (latch is coping to output regs<br /> <br /> * no event-by-event read, or need input pattern fifo ? or at least single sector pattern .. will discuss<br /> <br /> * control: gui on clonwin2, vxworks server; gui will save to file to be used during run<br /> <br /> * Ben's setup will stay<br /> <br /> * ECL output cards to be here soon<br /> <br /> * install CC and GUI on clonwin2<br /> <br /> * testing: self-test in Ben's office; cosmic etc tests to be planned<br /> <br /> * make sure level2 works with new electronics; single sector outputs from FPGA ? use L2 latch ? (it will be served as sector-based pattern as well ..)<br /> <br /> * pulser events and level2 ??????? want l2pass in that case ...<br /> <br /> * 2 test cables for Ben (68-68)<br /> <br /> * add EC to trigger ? extra 2 inputs per sector (inner and total from one discriminator, outer never used); will discuss again after L2 situation decided,<br /> may do not need 1-6 outputs as sector-based<br /> <br /> * install everything in the hall, start installation today; Valery and Raffaella will think about test plan using cosmic/pulser<br /> <br /> <br /> 2. G12 run: EPICS information in data stream, Raffaella will check it<br /> some fixes in DAQ (Sergey)<br /> EPICS expert ???<br /> <br /> <br /> 3. INFN will by TPC electronics</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_12,_2008_online_meeting_minutes&diff=3266 2008-03-12T14:56:07Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Ben Raydo, Sergey Pozdnyakov, Raffaella Devita, Valeri Kubarovski<br /> <br /> 1. G12 trigger<br /> <br /> * do not destroy existing trigger<br /> <br /> * new VME crate on top of trigger rack, all OR modules there, VME repeater<br /> <br /> * about 50 scalers, 2 reads by 16bit, every 10 seconds (latch is coping to output regs<br /> <br /> * no event-by-event read, or need input pattern fifo ? or at least single sector pattern .. will discuss<br /> <br /> * control: gui on clonwin2, vxworks server; gui will save to file to be used during run<br /> <br /> * Ben's setup will stay<br /> <br /> * ECL output cards to be here soon<br /> <br /> * install CC and GUI on clonwin2<br /> <br /> * testing: self-test in Ben's office; cosmic etc tests to be planned<br /> <br /> * make sure level2 works with new electronics; single sector outputs from FPGA ? use L2 latch ? (it will be served as sector-based pattern as well ..)<br /> <br /> * pulser events and level2 ??????? want l2pass in that case ...<br /> <br /> * 2 test cables for Ben (68-68)<br /> <br /> * add EC to trigger ? extra 2 inputs per sector (inner and total from one discriminator, outer never used)</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_12,_2008_online_meeting_minutes&diff=3265 2008-03-12T14:53:24Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Ben Raydo, Sergey Pozdnyakov, Raffaella Devita, Valeri Kubarovski<br /> <br /> 1. G12 trigger<br /> <br /> * do not destroy existing trigger<br /> <br /> * new VME crate on top of trigger rack, all OR modules there, VME repeater<br /> <br /> * about 50 scalers, 2 reads by 16bit, every 10 seconds (latch is coping to output regs<br /> <br /> * no event-by-event read, or need input pattern fifo ? or at least single sector pattern .. will discuss<br /> <br /> * control: gui on clonwin2, vxworks server; gui will save to file to be used during run<br /> <br /> * Ben's setup will stay<br /> <br /> * ECL output cards to be here soon<br /> <br /> * install CC and GUI on clonwin2<br /> <br /> * testing: self-test in Ben's office; cosmic etc tests to be planned<br /> <br /> * make sure level2 works with new electronics; single sector outputs from FPGA ? use L2 latch ? (it will be served as sector-based pattern as well ..)<br /> <br /> * pulser events and level2 ??????? want l2pass in that case ...<br /> <br /> * 2 test cables for Ben (68-68)<br /> <br /> * add EC to trigger ? extra 4 inputs per sector (inner and total, outer never used)</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_12,_2008_online_meeting_minutes&diff=3264 2008-03-12T14:50:45Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Ben Raydo, Sergey Pozdnyakov, Raffaella Devita, Valeri Kubarovski<br /> <br /> 1. G12 trigger<br /> <br /> * do not destroy existing trigger<br /> <br /> * new VME crate on top of trigger rack, all OR modules there, VME repeater<br /> <br /> * about 50 scalers, 2 reads by 16bit, every 10 seconds (latch is coping to output regs<br /> <br /> * no event-by-event read, or need input pattern fifo ? or at least single sector pattern .. will discuss<br /> <br /> * control: gui on clonwin2, vxworks server; gui will save to file to be used during run<br /> <br /> * Ben's setup will stay<br /> <br /> * ECL output cards to be here soon<br /> <br /> * install CC and GUI on clonwin2<br /> <br /> * testing: self-test in Ben's office; cosmic etc tests to be planned<br /> <br /> * make sure level2 works with new electronics; single sector outputs from FPGA ? use L2 latch ? (it will be served as sector-based pattern as well ..)<br /> <br /> * pulser events and level2 ??????? want l2pass in that case ...<br /> <br /> * 2 test cables for Ben (68-68)</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_12,_2008_online_meeting_minutes&diff=3263 2008-03-12T14:48:41Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Ben Raydo, Sergey Pozdnyakov, Raffaella Devita, Valeri Kubarovski<br /> <br /> 1. G12 trigger<br /> <br /> * do not destroy existing trigger<br /> <br /> * new VME crate on top of trigger rack, all OR modules there, VME repeater<br /> <br /> * about 50 scalers, 2 reads by 16bit, every 10 seconds (latch is coping to output regs<br /> <br /> * no event-by-event read, or need input pattern fifo ? or at least single sector pattern .. will discuss<br /> <br /> * control: gui on clonwin2, vxworks server; gui will save to file to be used during run<br /> <br /> * Ben's setup will stay<br /> <br /> * ECL output cards to be here soon<br /> <br /> * install CC and GUI on clonwin2<br /> <br /> * testing: self-test in Ben's office; cosmic etc tests to be planned<br /> <br /> * make sure level2 works with new electronics; single sector outputs from FPGA ? use L2 latch ? (it will be served as sector-based pattern as well ..)<br /> <br /> * pulser events and level2 ??????? want l2pass in that case ...</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_12,_2008_online_meeting_minutes&diff=3262 2008-03-12T14:47:25Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Ben Raydo, Sergey Pozdnyakov, Raffaella Devita, Valeri Kubarovski<br /> <br /> 1. G12 trigger<br /> <br /> * do not destroy existing trigger<br /> <br /> * new VME crate on top of trigger rack, all OR modules there, VME repeater<br /> <br /> * about 50 scalers, 2 reads by 16bit, every 10 seconds (latch is coping to output regs<br /> <br /> * no event-by-event read, or need input pattern fifo ? or at least single sector pattern .. will discuss<br /> <br /> * control: gui on clonwin2, vxworks server; gui will save to file to be used during run<br /> <br /> * Ben's setup will stay<br /> <br /> * ECL output cards to be here soon<br /> <br /> * install CC and GUI on clonwin2<br /> <br /> * testing: self-test in Ben's office; cosmic etc tests to be planned<br /> <br /> * make sure level2 works with new electronics; single sector outputs from FPGA ? use L2 latch ? (it will be served as sector-based pattern as well ..)<br /> <br /> * pulser events and level2 ???????</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_12,_2008_online_meeting_minutes&diff=3261 2008-03-12T14:42:27Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Ben Raydo, Sergey Pozdnyakov, Raffaella Devita, Valeri Kubarovski<br /> <br /> 1. G12 trigger<br /> <br /> * do not destroy existing trigger<br /> <br /> * new VME crate on top of trigger rack, all OR modules there, VME repeater<br /> <br /> * about 50 scalers, 2 reads by 16bit, every 10 seconds (latch is coping to output regs<br /> <br /> * no event-by-event read, or need input pattern fifo ? or at least single sector pattern .. will discuss<br /> <br /> * control: gui on clonwin2, vxworks server; gui will save to file to be used during run<br /> <br /> * Ben's setup will stay<br /> <br /> * ECL output cards to be here soon<br /> <br /> * install CC and GUI on clonwin2<br /> <br /> * testing: self-test in Ben's office; cosmic etc tests to be planned<br /> <br /> * make sure level2 works with new electronics; single sector outputs from FPGA ? use L2 latch ? (it will be served as sector-based pattern as well ..)</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_12,_2008_online_meeting_minutes&diff=3260 2008-03-12T14:34:47Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Ben Raydo, Sergey Pozdnyakov, Raffaella Devita, Valeri Kubarovski<br /> <br /> 1. G12 trigger<br /> <br /> * do not destroy existing trigger<br /> <br /> * new VME crate on top of trigger rack, all OR modules there, VME repeater<br /> <br /> * about 50 scalers, 2 reads by 16bit, every 10 seconds (latch is coping to output regs<br /> <br /> * no event-by-event read, or need input bitmask fifo ? or at least single sector pattern .. will discuss<br /> <br /> * control: gui on clonwin2, vxworks server; gui will save to file to be used during run<br /> <br /> * Ben's setup will stay<br /> <br /> * ECL output cards to be here soon<br /> <br /> * install CC and GUI on clonwin2<br /> <br /> * testing: self-test in Ben's office; cosmic etc tests to be planned</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_12,_2008_online_meeting_minutes&diff=3259 2008-03-12T14:00:19Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov,<br /> <br /> 1. G12 trigger<br /> <br /> * new VME crate on top of trigger rack, all OR modules there, VME repeated</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=March_12,_2008_online_meeting_minutes&diff=3258 2008-03-12T13:52:31Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov,</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=CLON_meeting_March_12,_2008&diff=3257 2008-03-12T00:39:36Z

<p>129.57.32.67: </p> <hr /> <div>Clas On-line Meeting, Wednesday, March 12 at 10am in Room A110<br /> ------------------------------------------------------------------<br /> <br /> 1. CLAS trigger system upgrade for G12 run<br /> <br /> 2. G12 preparation</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=CLON_Group_Meetings&diff=3256 2008-03-12T00:38:24Z

<p>129.57.32.67: </p> <hr /> <div>[[CLON meeting December 13, 2006]] &gt;&gt;&gt;&gt;&gt; [[December 13, 2006 online meeting minutes]]<br /> <br /> ==== 2007<br /> <br /> [[CLON meeting September 5, 2007]] &gt;&gt;&gt;&gt;&gt; [[September 5, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting September 12, 2007]] &gt;&gt;&gt;&gt;&gt; [[September 12, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting September 19, 2007]] &gt;&gt;&gt;&gt;&gt; [[September 19, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting September 26, 2007]] &gt;&gt;&gt;&gt;&gt; [[September 26, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting October 3, 2007]] &gt;&gt;&gt;&gt;&gt; [[October 3, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting October 10, 2007]] &gt;&gt;&gt;&gt;&gt; [[October 10, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting October 17, 2007]] &gt;&gt;&gt;&gt;&gt; [[October 17, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting October 24, 2007]] &gt;&gt;&gt;&gt;&gt; [[October 24, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting October 31, 2007]] &gt;&gt;&gt;&gt;&gt; [[October 31, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting November 7, 2007]] &gt;&gt;&gt;&gt;&gt; [[November 7, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting November 14, 2007]] &gt;&gt;&gt;&gt;&gt; [[November 14, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting November 28, 2007]] &gt;&gt;&gt;&gt;&gt; [[November 28, 2007 online meeting minutes]]<br /> <br /> [[CLON meeting December 12, 2007]] &gt;&gt;&gt;&gt;&gt; [[December 12, 2007 online meeting minutes]]<br /> <br /> ==== 2008<br /> <br /> [[CLON meeting January 16, 2008]] &gt;&gt;&gt;&gt;&gt; [[January 16, 2008 online meeting minutes]]<br /> <br /> [[CLON meeting January 23, 2008]] &gt;&gt;&gt;&gt;&gt; [[January 23, 2008 online meeting minutes]]<br /> <br /> [[CLON meeting January 30, 2008]] &gt;&gt;&gt;&gt;&gt; [[January 30, 2008 online meeting minutes]]<br /> <br /> [[CLON meeting February 13, 2008]] &gt;&gt;&gt;&gt;&gt; [[February 13, 2008 online meeting minutes]]<br /> <br /> [[CLON meeting March 5, 2008]] &gt;&gt;&gt;&gt;&gt; [[March 5, 2008 online meeting minutes]]<br /> <br /> [[CLON meeting March 12, 2008]] &gt;&gt;&gt;&gt;&gt; [[March 12, 2008 online meeting minutes]]</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=January_16,_2008_online_meeting_minutes&diff=3212 2008-01-16T16:19:20Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Sergey Pozdnyakov, Eugene Pasyuk<br /> <br /> '''G9A run status'''<br /> <br /> * TDC calibration run, analysis procedure is not operational yet<br /> * Pedestal run and analysis<br /> * run will be ended February 11 6am (Monday), next run will be G12 in April<br /> * need any 2-sector trigger for torus=0 run, it will be on bit 7<br /> * problem: EC HV mainframe 1 shuts itself down, have to go to the hall to turn it on; will open serial line and watch<br /> * network upgrade - crash - GPIB problems (firmware update ?)<br /> * ER crashed twice - very unusual, need to debug<br /> <br /> '''Projects status'''<br /> <br /> * new clonwiki machine was installed, it will contains clonwiki, inventory database front-end and maybe other documentation; currently not visible from outside<br /> <br /> * inventory database front-end was installed on clonwiki, under testing<br /> <br /> todo: brand link(s) to documentation, brand picture, check tag uniqueness (mysql primary key), make mysql to store history including<br /> person; make different users, some readonly; make maintenance history more advanced, remember date, locations, actions etc; cronjob on <br /> 'action needed'; minor fixes in other tables, sort by alphabet (in brand table by 3 fields, add 'edit' as well); make adjustable the number of <br /> records per page;sort every table by alphabet or date, up or down, by different columns; check in different browsers; ascii table will be <br /> primary source, until front-end is completely ready<br /> <br /> * HV patch panels have bad connectors, need to fix<br /> <br /> * repaires in progress</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=January_16,_2008_online_meeting_minutes&diff=3211 2008-01-16T16:18:39Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Sergey Pozdnyakov, Eugene Pasyuk<br /> <br /> '''G9A run status'''<br /> <br /> * TDC calibration run, analysis procedure is not operational yet<br /> * Pedestal run and analysis<br /> * run will be ended February 11 6am (Monday), next run will be G12 in April<br /> * need any 2-sector trigger for torus=0 run, it will be on bit 7<br /> * problem: EC HV mainframe 1 shuts itself down, have to go to the hall to turn it on; will open serial line and watch<br /> * network upgrade - crash - GPIB problems (firmware update ?)<br /> * ER crashed twice - very unusual, need to debug<br /> <br /> '''Projects status'''<br /> <br /> * new clonwiki machine was installed, it will contains clonwiki, inventory database front-end and maybe other documentation; currently not visible from outside<br /> <br /> * inventory database front-end was installed on clonwiki, under testing; todo: brand link(s) to documentation, brand picture, check tag uniqueness (mysql primary key), make mysql to store history including person; make different users, some readonly; make maintenance history more advanced, remember date, locations, actions etc; cronjob on 'action needed'; minor fixes in other tables, sort by alphabet (in brand table by 3 fields, add 'edit' as well); make adjustable the number of records per page;sort every table by alphabet or date, up or down, by different columns; check in different browsers; ascii table will be primary source, until front-end is completely ready<br /> <br /> * HV patch panels have bad connectors, need to fix<br /> <br /> * repaires in progress</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=January_16,_2008_online_meeting_minutes&diff=3210 2008-01-16T16:13:08Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Sergey Pozdnyakov, Eugene Pasyuk<br /> <br /> '''G9A run status'''<br /> <br /> * TDC calibration run, analysis procedure is not operational yet<br /> * Pedestal run and analysis<br /> * run will be ended February 11 6am (Monday), next run will be G12 in April<br /> * need any 2-sector trigger for torus=0 run, it will be on bit 7<br /> * problem: EC HV mainframe 1 shuts itself down, have to go to the hall to turn it on; will open serial line and watch<br /> * network upgrade - crash - GPIB problems (firmware update ?)<br /> * ER crashed twice - very unusual, need to debug<br /> <br /> '''Projects status'''<br /> <br /> * new clonwiki machine was installed, it will contains clonwiki, inventory database front-end and maybe other documentation; currently not visible from outside<br /> <br /> * inventory database front-end was installed on clonwiki, under testing<br /> add: brand link(s) to documentation, brand picture, check tag uniqueness (mysql primary key), make mysql to store history including person; make different users, some readonly; make maintenance history more advanced, remember date, locations, actions etc; cronjob on 'action needed'; minor fixes in other tables, sort by alphabet (in brand table by 3 fields, add 'edit' as well); make adjustable the number of records per page;sort every table by alphabet or date, up or down, by different columns; check in different browsers; ascii table will be primary source, until front-end is completely ready<br /> <br /> * HV patch panels have bad connectors, need to fix<br /> <br /> * repaires in progress</div>

129.57.32.67 https://clonwiki0.jlab.org/wiki/index.php?title=January_16,_2008_online_meeting_minutes&diff=3209 2008-01-16T16:08:22Z

<p>129.57.32.67: </p> <hr /> <div>present: Sergey Boyarinov, Sergey Pozdnyakov, Eugene Pasyuk<br /> <br /> '''G9A run status'''<br /> <br /> * TDC calibration run, analysis procedure is not operational yet<br /> * Pedestal run and analysis<br /> * run will be ended February 11 6am (Monday), next run will be G12 in April<br /> * need any 2-sector trigger for torus=0 run, it will be on bit 7<br /> * problem: EC HV mainframe 1 shuts itself down, have to go to the hall to turn it on; will open serial line and watch<br /> * network upgrade - crash - GPIB problems (firmware update ?)<br /> * ER crashed twice - very unusual, need to debug<br /> <br /> '''Projects status'''<br /> <br /> * new clonwiki machine was installed, it will contains clonwiki, inventory database front-end and maybe other documentation; currently not visible from outside<br /> <br /> * inventory database front-end was installed on clonwiki, under testing<br /> add: brand link(s) to documentation, brand picture, check tag uniqueness (mysql primary key), make mysql to store history including person; make different users, some readonly; make maintenance history more advanced, remember date, locations, actions etc; cronjob on 'action needed'; minor fixes in other tables, sort by alphabet (in brand table by 3 fields, add 'edit' as well); make adjustable the number of records per page;sort every table by alphabet or date, up or down, by different columns; check in different browsers<br /> <br /> * HV patch panels have bad connectors, need to fix<br /> <br /> * repaires in progress</div>

129.57.32.67